Three-dimensional Integrated Circuit Design (eBook)

Front Cover 1
Three-Dimensional Integrated Circuit Design 4
Copyright Page 5
Dedication Page 6
Contents 8
Preface 12
Acknowledgments 14
Chapter 1: Introduction 16
1.1. From the Integrated Circuit to the Computer 17
1.2. Interconnects, an Old Friend 20
1.3. Three-Dimensional or Vertical Integration 23
1.3.1. Opportunities for Three-Dimensional Integration 24
1.3.2. Challenges for Three-Dimensional Integration 26
1.4. Book Organization 28
Chapter 2: Manufacturing of 3-D Packaged Systems 32
2.1. Three-Dimensional Integration 32
2.1.1. System-in-Package 33
2.1.2. Three-Dimensional Integrated Circuits 33
2.2. System-on-Package 34
2.3. Technologies for System-in-Package 39
2.3.1. Wire-Bonded System-in-Package 39
2.3.2. Peripheral Vertical Interconnects 41
2.3.3. Area Array Vertical Interconnects 43
2.3.4. Metallizing the Walls of an SiP 45
2.4. Cost Issues for 3-D Integrated Systems 47
2.5. Summary 50
Chapter 3: 3-D Integrated Circuit Fabrication Technologies 52
3.1. Monolithic 3-D ICs 53
3.1.1. Stacked 3-D ICs 53
3.1.2. 3-D Fin-FETs 61
3.2. 3-D ICs with Through Silicon (TSV) or Interplane Vias 63
3.3. Contactless 3-D ICs 68
3.3.1. Capacitively Coupled 3-D ICs 68
3.3.2. Inductively Coupled 3-D ICs 70
3.4. Vertical Interconnects for 3-D ICs 71
3.4.1. Electrical Characteristics of Through Silicon Vias 76
3.5. Summary 78
Chapter 4: Interconnect Prediction Models 80
4.1. Interconnect Prediction Models for 2-D Circuits 81
4.2. Interconnect Prediction Models for 3-D ICs 84
4.3. Projections for 3-D ICs 88
4.4. Summary 92
Chapter 5: Physical Design Techniques for 3-D ICs 94
5.1. Floorplanning Techniques 94
5.1.1. Single-versus Multistep Floorplanning for 3-D ICs 96
5.1.2. Multi-Objective Floorplanning Techniques for 3-D ICs 99
5.2. Placement Techniques 102
5.2.1. Multi-Objective Placement for 3-D ICs 103
5.3. Routing Techniques 107
5.4. Layout Tools 110
5.5. Summary 112
Chapter 6: Thermal Management Techniques 114
6.1. Thermal Analysis of 3-D ICs 115
6.1.1. Closed-Form Temperature Expressions 116
6.1.2. Compact Thermal Models 123
6.1.3. Mesh-Based Thermal Models 125
6.2. Thermal Management Techniques without Thermal Vias 126
6.2.1. Thermal-Driven Floorplanning 126
6.2.2. Thermal-Driven Placement 132
6.3. Thermal Management Techniques Employing Thermal Vias 135
6.3.1. Region-Constrained Thermal Via Insertion 136
6.3.2. Thermal Via Planning Techniques 139
6.3.3. Thermal Wire Insertion 145
6.4. Summary 146
Chapter 7: Timing Optimization for Two-Terminal Interconnects 150
7.1. Interplane Interconnect Models 151
7.2. Two-Terminal Nets with a Single-Interplane Via 156
7.2.1. Elmore Delay Model of an Interplane Interconnect 156
7.2.2. Interplane Interconnect Delay 158
7.2.3. Optimum Via Location 160
7.2.4. Improvement in Interconnect Delay 163
7.3. Two-Terminal Interconnects with Multiple-Interplane Vias 166
7.3.1. Two-Terminal Via Placement Heuristic 170
7.3.2. Two-Terminal Via Placement Algorithm 174
7.3.3. Application of the Via Placement Technique 175
7.4. Summary 182
Chapter 8: Timing Optimization for Multiterminal Interconnects 184
8.1. Timing-Driven Via Placement for Interplane Interconnect Trees 184
8.2. Multiterminal Interconnect Via Placement Heuristics 188
8.2.1. Interconnect Trees 188
8.2.2. Single Critical Sink Interconnect Trees 189
8.3. Via Placement Algorithms for Interconnect Trees 191
8.3.1. Interconnect Tree Via Placement Algorithm (ITVPA) 191
8.3.2. Single Critical Sink Interconnect Tree Via Placement Algorithm (SCSVPA) 192
8.4. Via Placement Results and Discussion 192
8.5. Summary 198
Chapter 9: 3-D Circuit Architectures 200
9.1. Classification of Wire-Limited 3-D Circuits 201
9.2. Three-Dimensional Microprocessors and Memories 202
9.2.1. Three-Dimensional Microprocessor Logic Blocks 204
9.2.2. Three-Dimensional Design of Cache Memories 205
9.2.3. Architecting a 3-D Microprocessor - Memory System 210
9.3. Three-Dimensional Networks-on-Chip 212
9.3.1. 3-D NoC Topologies 213
9.3.2. Zero-Load Latency for 3-D NoC 215
9.3.3. Power Consumption in 3-D NoC 219
9.3.4. Performance and Power Analysis for 3-D NoC 221
9.3.5. Design Aids for 3-D NoCs 236
9.4. Three-Dimensional FPGAs 246
9.4.1. Design Aids for 3-D FPGAs 253
9.5. Summary 259
Chapter 10: Case Study: Clock Distribution Networks for 3-D ICs 262
10.1. MIT Lincoln Laboratories 3-D IC Fabrication Technology 263
10.2. 3-D Circuit Architecture 268
10.3. Clock Signal Distribution in 3-D Circuits 272
10.3.1. Timing Characteristics of Synchronous Circuits 273
10.3.2. Clock Distribution Network Structures within the Test Circuit 276
10.4. Experimental Results 280
10.5. Summary 287
Chapter 11: Conclusions 290
Appendix A: Enumeration of Gate Pairs in a 3-D IC 294
Appendix B: Formal Proof of Optimum Single Via Placement 296
Appendix C: Proof of the Two-terminal Via Placement Heuristic 298
Appendix D: Proof of Condition for Via Placement of Multiterminal Nets 302
References 304
Index 320