Power Distribution Networks with On-Chip Decoupling Capacitors (eBook)

Contents 8
1 Preface to the Second Edition 20
2 Preface to the First Edition 24
Part I General Background 28
1 Introduction 31
1.1 Evolution of integrated circuit technology 33
1.2 Evolution of design objectives 36
1.3 The problem of power distribution 40
1.4 Deleterious effects of power distribution noise 46
1.4.1 Signal delay uncertainty 47
1.4.2 On-chip clock jitter 47
1.4.3 Noise margin degradation 50
1.4.4 Degradation of gate oxide reliability 50
1.5 Summary 51
2 Inductive Properties of Electric Circuits 52
2.1 Definitions of inductance 53
2.1.1 Field energy definition 53
2.1.2 Magnetic flux definition 55
2.1.3 Partial inductance 60
2.1.4 Net inductance 65
2.2 Variation of inductance with frequency 68
2.2.1 Uniform current density approximation 69
2.2.2 Inductance variation mechanisms 70
Skin effect 70
Proximity effect 70
Multi-path current redistribution 72
2.2.3 Simple circuit model 74
2.3 Inductive behavior of circuits 77
2.4 Inductive properties of on-chip interconnect 79
2.5 Summary 83
3 Properties of On-Chip Inductive Current Loops 84
3.1 Introduction 84
3.2 Dependence of inductance on line length 85
3.3 Inductive coupling between two parallel loop segments 92
3.4 Application to circuit analysis 93
3.5 Summary 94
4 Electromigration 96
4.1 Physical mechanism of electromigration 97
4.2 Electromigration-induced mechanical stress 100
4.3 Steady state limit of electromigration damage 101
4.4 Dependence of electromigration lifetime on the line dimensions 103
4.5 Statistical distribution of electromigration lifetime 106
4.6 Electromigration lifetime under AC current 107
4.7 A comparison of aluminum and copper interconnect technologies 108
4.8 Designing for electromigration reliability 111
4.9 Summary 111
5 Decoupling Capacitance 113
5.1 Introduction to decoupling capacitance 114
5.1.1 Historical retrospective 114
5.1.2 Decoupling capacitor as a reservoir of charge 115
5.1.3 Practical model of a decoupling capacitor 117
5.2 Impedance of power distribution system with decoupling capacitors 121
5.2.1 Target impedance of a power distribution system 121
5.2.2 Antiresonance 124
5.2.3 Hydraulic analogy of hierarchical placement of decoupling capacitors 128
Fully compensated system 132
5.3 Intrinsic vs intentional on-chip decoupling capacitance 133
5.3.1 Intrinsic decoupling capacitance 134
5.3.2 Intentional decoupling capacitance 138
5.4 Types of on-chip decoupling capacitors 140
5.4.1 Polysilicon-insulator-polysilicon (PIP) capacitors 141
5.4.2 MOS capacitors 143
Accumulation 145
Depletion 146
Inversion 147
5.4.3 Metal-insulator-metal (MIM) capacitors 151
5.4.4 Lateral flux capacitors 153
Fractal capacitors 153
Woven capacitors 156
Vertical parallel plate (VPP) capacitors 156
5.4.5 Comparison of on-chip decoupling capacitors 157
5.5 On-chip switching voltage regulator 159
5.6 Summary 161
6 Scaling Trends of On-Chip Power Distribution Noise 163
6.1 Scaling models 164
6.2 Interconnect characteristics 166
6.2.1 Global interconnect characteristics 168
6.2.2 Scaling of the grid inductance 168
6.2.3 Flip-chip packaging characteristics 169
6.2.4 Impact of on-chip capacitance 171
6.3 Model of power supply noise 172
6.4 Power supply noise scaling 174
6.4.1 Analysis of constant metal thickness scenario 174
6.4.2 Analysis of the scaled metal thickness scenario 175
6.4.3 ITRS scaling of power noise 177
6.5 Implications of noise scaling 181
6.6 Summary 182
7 Conclusions 183
Part II Design of Power Systems 184
8 High Performance Power Distribution Systems 187
8.1 Physical structure of a power distribution system 188
8.2 Circuit model of a power distribution system 189
8.3 Output impedance of a power distribution system 192
8.4 A power distribution system with a decoupling capacitor 195
8.4.1 Impedance characteristics 195
8.4.2 Limitations of a single-tier decoupling scheme 199
8.5 Hierarchical placement of decoupling capacitance 201
Board decoupling capacitors 201
Package decoupling capacitors 202
On-chip decoupling capacitors 205
Advantages of hierarchical decoupling 205
8.6 Resonance in power distribution networks 208
8.7 Full impedance compensation 214
8.8 Case study 216
8.9 Design considerations 219
8.9.1 Inductance of the decoupling capacitors 219
8.9.2 Interconnect inductance 220
8.10 Limitations of the one-dimensional circuit model 221
8.11 Summary 224
9 On-Chip Power Distribution Networks 225
9.1 Styles of on-chip power distribution networks 226
9.1.1 Basic structure of on-chip power distribution networks 226
Routed networks 226
Mesh networks 226
Grid structured networks 227
Power and ground planes 229
Cascaded power/ground rings 230
Hybrid-structured networks 230
9.1.2 Improving the impedance characteristics of on-chip power distribution networks 231
9.1.3 Evolution of power distribution networks in Alpha microprocessors 232
Alpha 21064 233
Alpha 21164 233
Alpha 21264 234
9.2 Die-package interface 234
Wire-bond packaging 235
Flip-chip packaging 236
Future packaging solutions 239
9.3 Other considerations 239
Dependence of on-chip signal integrity on the structure of the power distribution network 240
Interaction between the substrate and the power distribution network 240
9.4 Summary 241
10 Computer-Aided Design and Analysis 242
10.1 Design flow for on-chip power distribution networks 243
Preliminary pre-floorplan design 243
Floorplan-based refinement 245
Layout-based verification 246
10.2 Linear analysis of power distribution networks 248
10.3 Modeling power distribution networks 250
Resistance of the on-chip power distribution network 251
Characterization of the on-chip decoupling capacitance 252
Inductance of the on-chip power distribution network 253
Exploiting symmetry to reduce model complexity 255
10.4 Characterizing the power current requirements of on-chip circuits 257
Preliminary evaluation of power current requirements 257
Gate level estimates of the power current requirements 258
10.5 Numerical methods for analyzing power distribution networks 259
Model partitioning in RC and RLC parts 260
Improving the initial condition accuracy of the AC analysis 260
Global-local hierarchical analysis 262
Random walk based technique 264
Multigrid analysis 265
Hierarchical analysis of networks with mesh-tree topology 265
Efficient analysis of RL trees 266
10.6 Allocation of on-chip decoupling capacitors 266
10.6.1 Charge-based allocation methodology 268
10.6.2 Allocation strategy based on the excessive noise amplitude 269
10.6.3 Allocation strategy based on excessive charge 270
10.7 Summary 272
11 Closed-Form Expressions for Fast IR Drop Analysis 274
11.1 Background of FAIR 275
11.2 Analytic IR drop analysis 277
11.2.1 One power supply and one current load 278
11.2.2 One power supply and multiple current loads 280
11.2.3 Multiple power supplies and one current load 281
11.2.4 Multiple power supplies and multiple current loads 284
11.3 Locality in power grid analysis 286
11.3.1 Principle of spatial locality in a power grid 286
11.3.2 Effect of spatial locality on computational complexity 290
11.3.3 Exploiting spatial locality in FAIR 291
11.3.4 Error correction windows 292
11.4 Experimental results 293
11.5 Summary 297
12 Conclusions 299
Part III Noise in Power Distribution Networks 300
13 Inductive Properties of On-Chip Power Distribution Grids 303
13.1 Power transmission circuit 303
13.2 Simulation setup 306
13.3 Grid types 306
13.4 Inductance versus line width 311
13.5 Dependence of inductance on grid type 312
13.5.1 Non-interdigitated versus interdigitated grids 312
13.5.2 Paired versus interdigitated grids 313
13.6 Dependence of Inductance on grid dimensions 314
13.6.1 Dependence of inductance on grid width 314
13.6.2 Dependence of inductance on grid length 316
13.6.3 Sheet inductance of power grids 316
13.6.4 Efficient computation of grid inductance 317
13.7 Summary 319
14 Variation of Grid Inductance with Frequency 320
14.1 Analysis approach 320
14.2 Discussion of inductance variation 322
14.2.1 Circuit models 322
14.2.2 Analysis of inductance variation 325
14.3 Summary 327
15 Inductance/Area/Resistance Tradeoffs 329
15.1 Inductance vs. resistance tradeoff under a constant grid area constraint 329
15.2 Inductance vs. area tradeoff under a constant grid resistance constraint 334
15.3 Summary 336
16 Inductance Model of Interdigitated Power and Ground Distribution Networks 338
16.1 Basic four-pair structure 339
16.2 Power and ground distribution network with a large number of interdigitated pairs 340
16.3 Comparison and discussion 345
16.4 Summary 349
17 On-Chip Power Noise Reduction Techniques 351
17.1 Ground noise reduction through an additional low noise on-chip ground 353
17.2 Dependence of ground bounce reduction on system parameters 355
17.2.1 Physical separation between noisy and noise sensitive circuits 356
17.2.2 Frequency and capacitance variations 357
17.2.3 Impedance of an additional ground path 359
17.3 Summary 360
18 Noise Issues in On-Chip Power Distribution Networks 362
18.1 Scaling effects in chip-package resonance 363
18.2 Propagation of power distribution noise 365
18.3 Local inductive behavior 368
18.4 Summary 372
19 Conclusions 373
Part IV Placement of On-Chip Decoupling Capacitance 374
20 Effective Radii of On-Chip Decoupling Capacitors 377
20.1 Background 379
20.2 Effective radius of on-chip decoupling capacitor based on target impedance 381
20.3 Estimation of required on-chip decoupling capacitance 383
20.3.1 Dominant resistive noise 384
20.3.2 Dominant inductive noise 385
20.3.3 Critical line length 388
20.4 Effective radius as determined by charge time 390
20.5 Design methodology for placing on-chip decoupling capacitors 396
20.6 Model of on-chip power distribution network 396
20.7 Case study 399
20.8 Design implications 405
20.9 Summary 406
21 Efficient Placement of Distributed On-Chip Decoupling Capacitors 408
21.1 Technology constraints 409
21.2 Placing on-chip decoupling capacitors in nanoscale ICs 410
21.3 Design of a distributed on-chip decoupling capacitor network 413
21.4 Design tradeoffs in a distributed on-chip decoupling capacitor network 418
21.4.1 Dependence of system parameters on R1 419
21.4.2 Minimum C1 420
21.4.3 Minimum total budgeted on-chip decoupling capacitance 421
21.5 Design methodology for a system of distributed on-chip decoupling capacitors 423
21.6 Case study 426
21.7 Summary 430
22 Simultaneous Co-Design of Distributed On-Chip Power Supplies and Decoupling Capacitors 432
22.1 Problem formulation 434
22.2 Simultaneous power supply and decoupling capacitor placement 435
22.3 Case study 437
22.4 Summary 441
23 Conclusions 442
Part V Multi-Layer Power Distribution Networks 443
24 Impedance Characteristics of Multi-Layer Grids 445
24.1 Electrical properties of multi-layer grids 447
24.1.1 Impedance characteristics of individual grid layers 447
24.1.2 Impedance characteristics of multi-layer grids 450
24.2 Case study of a two layer grid 452
24.2.1 Simulation setup 453
24.2.2 Inductive coupling between grid layers 453
24.2.3 Inductive characteristics of a two layer grid 457
24.2.4 Resistive characteristics of a two layer grid 458
24.2.5 Variation of impedance with frequency in a two layer grid 460
24.3 Design implications 461
24.4 Summary 462
25 Multi-Layer Interdigitated Power Distribution Networks 464
25.1 Single metal layer characteristics 466
25.1.1 Optimal width for minimum impedance 468
25.1.2 Optimal width characteristics 471
25.2 Multi-layer optimization 474
25.2.1 First approach - equal current density 475
25.2.2 Second approach - minimum impedance 481
25.3 Discussion 483
25.3.1 Comparison 483
25.3.2 Routability 484
25.3.3 Fidelity 487
25.3.4 Critical frequency 488
25.4 Summary 489
26 Conclusions 491
Part VI Multi-Voltage Power Network Systems 492
27 Multiple On-Chip Power Supply Systems 494
27.1 ICs with multiple power supply voltages 495
27.1.1 Multiple power supply voltage techniques 496
27.1.2 Clustered voltage scaling (CVS) 498
27.1.3 Extended clustered voltage scaling (ECVS) 499
27.2 Challenges in ICs with multiple power supply voltages 500
27.2.1 Die area 501
27.2.2 Power dissipation 501
27.2.3 Design complexity 502
27.2.4 Placement and routing 502
Area-by-area architecture 503
Row-by-row architecture 503
In-row architecture 503
27.3 Optimum number and magnitude of available power supply voltages 505
27.4 Summary 510
28 On-Chip Power Distribution Grids with Multiple Supply Voltages 512
28.1 Background 514
28.2 Simulation setup 515
28.3 Power distribution grid with dual supply and dual ground 517
28.4 Interdigitated grids with DSDG 520
28.4.1 Type I interdigitated grids with DSDG 520
28.4.2 Type II interdigitated grids with DSDG 522
28.5 Paired grids with DSDG 524
28.5.1 Type I paired grids with DSDG 525
28.5.2 Type II paired grids with DSDG 526
28.6 Simulation results 529
28.6.1 Interdigitated power distribution grids without decoupling capacitors 530
28.6.2 Paired power distribution grids without decoupling capacitors 537
28.6.3 Power distribution grids with decoupling capacitors 538
28.6.4 Dependence of power noise on the switching frequency of the current loads 542
28.7 Design implications 545
28.8 Summary 547
29 Decoupling Capacitors for Multi-Voltage Power Distribution Systems 549
29.1 Impedance of a power distribution system 551
29.1.1 Impedance of a power distribution system 552
29.1.2 Antiresonance of parallel capacitors 555
29.1.3 Dependence of impedance on power distribution system parameters 556
29.2 Case study of the impedance of a power distribution system 559
29.3 Voltage transfer function of power distribution system 564
29.3.1 Voltage transfer function of a power distribution system 564
29.3.2 Dependence of voltage transfer function on power distribution system parameters 566
29.4 Case study of the voltage response of a power distribution system 569
29.4.1 Overshoot-free magnitude of a voltage transfer function 571
29.4.2 Tradeoff between the magnitude and frequency range 573
29.5 Summary 577
30 Conclusions 578
Part VII Final Comments and Supplementary Material 579
Closing Remarks 580
Appendices 585
A Estimate of Initial Optimal Width for Interdigitated Power/Ground Network 586
B First Optimization Approach for Multi-Layer Interdigitated Power Distribution Network 587
C Second Optimization Approach for Multi-Layer Interdigitated Power Distribution Network 589
D Mutual Loop Inductance in Fully Interdigitated Power Distribution Grids with DSDG 590
E Mutual Loop Inductance in Pseudo-Interdigitated Power Distribution Grids with DSDG 592
F Mutual Loop Inductance in Fully Paired Power Distribution Grids with DSDG 594
G Mutual Loop Inductance in Pseudo-Paired Power Distribution Grids with DSDG 596
References 598
Index 626
About the Authors 631