ESL Models and their Application (eBook)
XXIV, 446 Seiten
Springer US (Verlag)
978-1-4419-0965-7 (ISBN)
This book arises from experience the authors have gained from years of work as industry practitioners in the field of Electronic System Level design (ESL). At the heart of all things related to Electronic Design Automation (EDA), the core issue is one of models: what are the models used for, what should the models contain, and how should they be written and distributed. Issues such as interoperability and tool transportability become central factors that may decide which ones are successful and those that cannot get sufficient traction in the industry to survive.
Through a set of real examples taken from recent industry experience, this book will distill the state of the art in terms of System-Level Design models and provide practical guidance to readers that can be put into use. This book is an invaluable tool that will aid readers in their own designs, reduce risk in development projects, expand the scope of design projects, and improve developmental processes and project planning.
This book arises from experience the authors have gained from years of work as industry practitioners in the field of Electronic System Level design (ESL). At the heart of all things related to Electronic Design Automation (EDA), the core issue is one of models: what are the models used for, what should the models contain, and how should they be written and distributed. Issues such as interoperability and tool transportability become central factors that may decide which ones are successful and those that cannot get sufficient traction in the industry to survive.Through a set of real examples taken from recent industry experience, this book will distill the state of the art in terms of System-Level Design models and provide practical guidance to readers that can be put into use. This book is an invaluable tool that will aid readers in their own designs, reduce risk in development projects, expand the scope of design projects, and improve developmental processes and project planning.
Preface 4
Who Should Read This Book 5
Structure of the Book 6
Chapter Listing 7
Relationship to First Book 9
Companion Web Site 9
Reference 10
Acknowledgments 11
Contents 12
About the Authors 18
About the Contributors 20
1 Introduction 22
1.1 A Definition of a Model 22
1.2 A Day in the Life of a Model 5
1.3 Types of Model 6
1.4 Models of Computation 7
1.5 Simplification 9
1.5.1 Abstraction 31
1.5.2 Structure 31
1.6 Models and Languages 33
1.6.1 Imperative Languages 33
1.6.2 Declarative Languages 34
1.6.3 Functional 35
1.6.4 Non-functional 36
1.6.5 Meta 37
1.6.6 Testbench 38
1.7 The Desire for a New Language 39
1.8 Big Shoes to Fill 40
1.8.1 Ptolemy Simulator 41
1.8.2 SystemC 42
1.8.3 Function and Interface 43
1.9 Taxonomy 43
1.9.1 Three New Axes 44
1.9.1.1 Concurrency 44
1.9.1.2 Communications 45
1.9.1.3 Configurability 45
1.9.2 Application to Models and Languages 46
1.9.3 Transformation of Models 48
1.10 Definitions 49
References 52
2 IP Meta-Models for SoC Assembly and HW/SW Interfaces 54
2.1 Introduction 54
2.2 IP Databases 54
2.3 SPIRIT/IP-XACT 55
2.3.1 History of SPIRIT 55
2.3.2 RTL Assembly Level 58
2.3.3 System Modeling Level 62
2.4 Register Definition Languages 62
2.4.1 Motivation: Modeling the HW/SW Interface 63
2.4.1.1 What Is the HW/SW Interface? 63
2.4.1.2 Hardware Configuration and Control Using Software 64
2.4.1.3 Software Perspective 65
2.4.1.4 Interrupts 67
2.4.1.5 Software API 67
2.4.1.6 Hardware Perspective 68
2.4.1.7 Transaction Bus Protocol 69
2.4.1.8 Protocol Translation 70
2.4.1.9 Registers and Bitfields 72
2.4.2 HW/SW Design Flow for HW/SW Interfaces 77
2.4.2.1 Example IP Design -- The Requirements 78
2.4.2.2 Specification -- Documentation 79
2.4.2.3 IP-XACT (SPIRIT) 79
2.4.2.4 SystemRDL 81
2.4.2.5 IP Hardware Design 81
2.4.2.6 IP Verification 84
2.4.2.7 HDL Verification Environments 85
2.4.2.8 HVL Environments 85
2.4.2.9 VMM -- Verification Methodology Manual 86
2.4.2.10 OVM -- Open Verification Methodology 87
2.4.2.11 eRM '' Specman ''e'' Reuse Methodology 88
2.4.2.12 OVM vs. VMM Interoperability 88
2.4.2.13 Chip-Level Verification 88
2.4.2.14 Software Development -- Firmware 91
2.4.2.15 Firmware Verification 93
2.4.2.16 RTL Models 94
2.4.2.17 Virtual Models 94
2.4.2.18 Earlier Software Development 94
2.4.3 Emerging HW/SW Interface Tools and Design Flows 95
2.4.3.1 Register Management Tools 96
2.4.3.2 Case Study of a Register Management Solution: Bitwise 98
2.5 Conclusions 101
References 102
3 Functional Models 104
3.1 Dynamic Models and Languages 104
3.1.1 Algorithmic Languages 105
3.1.1.1 Mathematical Modeling Languages 105
3.1.1.2 Example of MATLAB 106
3.1.1.3 Example of C/C++ Reference Model 108
3.1.1.4 Dataflow Modeling Languages 109
3.1.1.5 Example of Simulink 110
3.1.2 Architectural Modeling Languages: SystemC 112
3.1.2.1 Scope of SystemC: Design Problems 112
3.1.2.2 SystemC 2.0 114
3.1.2.3 SystemC Language Basics 114
3.1.2.4 SystemC in Real Systems 122
3.1.2.5 Software System Specification 134
3.1.2.6 TLM 2.0 138
3.1.2.7 TLM Compliance Checking 149
3.1.3 Architectural Models 155
3.1.3.1 Modeling IP 155
3.1.3.2 System Models for Architectural Exploration 156
3.1.3.3 System Models for Software Development 158
3.2 Formal Models 158
3.2.1 Property Languages 158
3.2.1.1 Uses of Declarative Languages 159
3.2.1.2 Completeness 160
References 162
4 Testbench Models 163
4.1 Testbench Basics 164
4.1.1 Testbench Components 166
4.1.1.1 Verification Plan 167
4.1.1.2 Comparison Model 167
4.1.1.3 Progress Model 168
4.1.1.4 Input Constraints Model 168
4.1.2 Verification Methodologies 169
4.1.3 Verification IP 172
4.2 Verification Plan 172
4.3 Comparison Model 177
4.3.1 Testbench Languages 178
4.4 Progress Model 181
4.4.1 Ad Hoc Metrics 181
4.4.2 Structural Metrics 181
4.4.3 Functional Metrics 182
4.4.4 Coverage Metrics in SystemC 182
4.4.4.1 Simple Code Coverage 183
4.4.4.2 SystemC Verification Library 183
4.4.5 Coverage Metrics in SystemVerilog 185
4.5 Input Constraints 186
4.6 Verification IP 188
4.6.1 VIP Components 189
4.6.2 VIP Standardization 190
4.7 Conclusions 190
References 191
5 Virtual Prototypes and Mixed Abstraction Modeling 193
5.1 Introduction 195
5.1.1 Historical Perspective 196
5.1.2 Use Models 199
5.1.2.1 Early Verification and Validation 199
5.1.2.2 Architectural Analysis 200
5.1.2.3 Software Development 201
5.1.2.4 Debug and Visibility 202
5.1.3 Technology 203
5.1.3.1 Taxonomy 203
5.1.3.2 Time Advancement 207
5.1.4 Interfaces 207
5.1.5 Processor Models 208
5.2 System Prototypes 211
5.2.1 Development Environments for Software Development 211
5.2.2 Hybrid Hardware--Software-Based Development Platforms 213
5.2.3 Hybrid System Prototyping Use Models 214
5.3 Constructing a System-Level Virtual Prototype 214
5.3.1 Modeling Languages 216
5.3.1.1 SystemC 216
5.3.1.2 Magic-C 217
5.3.1.3 VRE C++ 219
5.3.2 Model Creation 220
5.3.3 Model Import 221
5.3.4 Model Libraries 221
5.3.5 Virtual Devices 222
5.3.6 Modeling the Environment 224
5.3.7 Tying It All Together 225
5.3.8 Documentation 225
5.4 Running the Prototype 225
5.4.1 Debug 227
5.4.2 Analysis 228
5.4.2.1 Power Analysis 233
5.5 Verification 234
5.5.1 Platform Deployment 234
5.5.2 Verification Methodology Manual 235
5.5.3 Building the RTL Testbench 236
5.5.4 Regressions 237
5.6 Example 238
5.6.1 The Application 239
5.6.2 The Bottom Line 242
5.7 The Future 243
References 244
6 Processor-Centric Design: Processors, Multi-Processors, and Software 245
6.1 Choices and Trade-Offs in Processor-Centric Design 245
6.2 An ASIP Integrated Development Environment (IDE) 249
6.3 Introduction to Flow and Example 252
6.4 Starting with Algorithms 254
6.5 Processor Definition 254
6.5.1 Designing the Design Space Exploration 254
6.5.2 Exploring the Processor Design Space: Preconfigured Cores 256
6.5.3 Exploring the Processor Design Space: Automatically 260
6.5.4 Exploring the Processor Design Space: Cache and Memory 268
6.5.5 Exploring the Processor Design Space: Fine-Tuning 269
6.5.6 Speed--Area--Power Trade-offs 272
6.5.7 Detailed Energy Space Exploration 275
6.6 Software Implementation 276
6.7 Predicting Software Performance via Sampling 278
6.8 Multicore Issues 279
6.8.1 A Practical Methodology for Multi-processor ASIP Definition and Programming 282
6.8.2 Developing Multicore System-Level Models 285
6.8.3 Porting Methodology for New Video Codecs to the Multicore system 285
6.8.4 Using the IDE for Multicore Simulation and Validation 287
6.9 Debug 288
6.9.1 Single-Core Debug in the IDE 288
6.9.2 Multi-processor Debug in the IDE 288
6.10 Conclusions 292
References 292
7 Codesign Experiences Based on a Virtual Platform 293
7.1 Introduction 293
7.2 Virtual Platforms 294
7.2.1 Introduction 294
7.2.2 Evolution of Platform Complexity 294
7.2.3 Methodologies 295
7.2.4 Commercial Technologies for Virtual Platform Development 297
7.2.5 Models of Computation 300
7.3 Platform and Application Description 300
7.3.1 System Specification and Functional Verification 302
7.3.2 Architectural Exploration 304
7.3.2.1 Definition and Configuration 305
7.3.2.2 Moving Modules Between Hardware and Software Partitions on a Multi-bus Architecture 308
7.3.2.3 ISS Abstraction 309
7.3.3 Analysis 312
7.3.3.1 User Module Computation and RTOS Computation 314
7.3.3.2 User Module Communication 315
7.3.3.3 Bus Usage 315
7.3.4 Integration 317
7.3.4.1 Interface Synthesis 317
7.3.4.2 Behavioral Synthesis 317
7.3.4.3 Platform Synthesis 319
7.4 Experiments 320
7.4.1 Pipelined vs. Non-pipelined Models 320
7.4.2 Architectural Exploration of the JPEG Decoder 322
7.5 Conclusion 325
References 327
8 Transaction-Level Platform Creation 329
8.1 Introduction 329
8.2 Transaction-Level Modeling Comes of Age 330
8.3 Model Abstractions 332
8.3.1 Terminology 332
8.3.2 Model Taxonomy 333
8.4 Roles of the TLM Platform 335
8.5 Contextual Verification 337
8.6 Creating Models 339
8.6.1 Model Refinement 340
8.6.2 Multi-abstraction 343
8.6.2.1 SystemVerilog DPI 344
8.6.2.2 Transactor Models 344
8.6.3 Verification 345
8.6.3.1 Verifying the System Model 346
8.6.3.2 Using the System Model for RTL Verification 347
8.7 Timing 353
8.7.1 Timing Policies 355
8.7.2 Delay 355
8.7.3 Split 356
8.7.4 Sequential 357
8.7.5 Pipelining 358
8.7.6 Putting It All Together 359
8.7.7 Timing Callbacks 361
8.8 Power 362
8.9 Creating a Model 362
8.9.1 Using Model Builder 362
8.9.2 Synchronization 365
8.9.3 Integrating 3rd party Models 366
8.9.4 Model Abstraction 366
8.9.5 Building a System 366
8.9.6 Navigating a System 367
8.10 Example 368
8.10.1 Building the System 370
8.10.2 Running the Simulation 371
8.10.3 Analyzing the System 374
8.10.4 Inserting an ISS Model 376
8.11 Conclusions 378
References 379
9 C/C++ Hardware Design for the Real World 380
9.1 Introduction 380
9.1.1 Chapter Overview 381
9.2 Where Does It Fit in an ESL Flow 382
9.2.1 Hardware Implementation Input 384
9.2.2 High-Level Synthesis Output 386
9.2.3 Verification Models 387
9.2.4 Other Uses for the Input Model 388
9.3 Why C/C++/SystemC 388
9.3.1 Language Limitations for Synthesis 391
9.4 High-Level Synthesis Fundamentals 392
9.4.1 Schedule and Allocation Trade-offs 392
9.4.2 Synthesis at the Interface 394
9.4.3 Hierarchy 394
9.4.4 Other Control 395
9.4.5 Target Library 397
9.4.6 Data-Type Libraries for Synthesis 397
9.4.7 Synthesis Tools 401
9.4.7.1 The Gantt Chart 401
9.4.7.2 Datapath Diagram 402
9.4.7.3 Interactive Exploration 403
9.5 Synthesis Domains 403
9.6 A Simple Example 404
9.6.1 Embedded Architecture 405
9.7 Tying It into a Verification Flow 411
9.7.1 Verification with Simulation 411
9.7.2 Verification with Equivalence Checking 413
9.7.3 Verification Against Algorithmic Model 413
9.7.4 Verifying Power 415
9.8 A More Complex Example 415
9.8.1 The Application 417
9.8.2 The Flow 418
9.8.3 Design 419
9.8.3.1 Step 1: Research Phase 419
9.8.3.2 Step 2: Pick a Solution 419
9.8.3.3 Step 3: Code the Algorithm 421
9.8.3.4 Step 4: Taking Care with I/O Ports 427
9.8.3.5 Step 5: Dealing with the Inverse Square Root 430
9.8.4 Verification 434
9.8.5 Synthesis 436
9.8.5.1 Synthesizing the Square Root 436
9.8.5.2 Manipulating Variables and Resources 437
9.8.5.3 Synthesizing the QR Block 438
9.8.6 Results 442
9.8.7 Results Analysis 444
9.9 Successful Adoption 445
9.10 The Future 447
9.11 Summary 448
References 449
Acronyms 452
Index 456
| Erscheint lt. Verlag | 15.12.2009 |
|---|---|
| Reihe/Serie | Embedded Systems |
| Zusatzinfo | XXIV, 446 p. 177 illus. |
| Verlagsort | New York |
| Sprache | englisch |
| Themenwelt | Mathematik / Informatik ► Informatik ► Programmiersprachen / -werkzeuge |
| Mathematik / Informatik ► Informatik ► Theorie / Studium | |
| Informatik ► Weitere Themen ► CAD-Programme | |
| Technik ► Elektrotechnik / Energietechnik | |
| Schlagworte | ASIC • Automat • EDA • Electronic Design Automation • electronic system level • ESL • FPGA • Hardware • Integrated circuit • Multicore • single-electron transistor • system level design • System on chip (SoC) • testbenches • verification |
| ISBN-10 | 1-4419-0965-6 / 1441909656 |
| ISBN-13 | 978-1-4419-0965-7 / 9781441909657 |
| Haben Sie eine Frage zum Produkt? |
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