Wafer Level 3-D ICs Process Technology (eBook)
XII, 410 Seiten
Springer US (Verlag)
978-0-387-76534-1 (ISBN)
This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.
Three-dimensional (3D) integration is clearly the simplest answer to most of the semiconductor industry's vexing problems: heterogeneous integration and red- tions of power, form factor, delay, and even cost. Conceptually the power, latency, and form factor of a system with a ?xed number of transistors all scale roughly linearly with the diameter of the smallest sphere enclosing frequently interacting devices. This clearly provides the fundamental motivation behind 3D technologies which vertically stack several strata of device and interconnect layers with high vertical interconnectivity. In addition, the ability to vertically stack strata with - vergent and even incompatible process ?ows provides for low cost and low parasitic integration of diverse technologies such as sensors, energy scavengers, nonvolatile memory, dense memory, fast memory, processors, and RF layers. These capabilities coupled with today's trends of increasing levels of integrated functionality, lower power, smaller form factor, increasingly divergent process ?ows, and functional diversi?cation would seem to make 3D technologies a natural choice for most of the semiconductor industry. Since the concept of vertical integration of different strata has been around for over 20 years, why aren't vertically stacked strata endemic to the semiconductor industry? The simple answer to this question is that in the past, the 3D advantages while interesting were not necessary due to the tremendous opportunities offered by geometric scaling. In addition, even when the global interconnect problem of high-performance single-core processors seemed insurmountable without inno- tions such as 3D, alternative architectural solutions such as multicores could eff- tivelydelaybutnoteliminatetheneedfor3D.
Foreword 6
Preface 8
Contents 10
Contributors 12
1 Overview of Wafer-Level 3D ICs 16
1.1 Background and Introduction 16
1.2 Motivations -- A More than Moore Approach 18
1.2.1 Interconnect Bottleneck 18
1.2.2 Chip Form Factor 19
1.2.3 Heterogeneous Integration 19
1.2.4 Stacked CMOS 19
1.3 Classification of 3D ICs 20
1.3.1 Monolithic Approaches 21
1.3.2 Assembly Approaches 21
1.3.3 Wafer-Level 3D Design Opportunities 23
1.4 Organization of the Book 24
2 Monolithic 3D Integrated Circuits 27
2.1 Introduction 27
2.2 Three-Dimensional Circuits Using Large-Grain Upper Layers 28
2.2.1 Upper-Layer Recrystallization Techniques 28
2.2.1.1 Laser Recrystallization 28
2.2.1.2 Epitaxial Overgrowth and Solid-Phase Crystallization 29
2.2.2 Three-Dimensional Logic Process Architectures 30
2.2.2.1 Common-Gate Processes 30
2.2.2.2 Independent Gate Processes 31
2.3 Three-Dimensional Circuits Using Small-Grained Polysilicon Layers 33
2.3.1 SRAM 33
2.3.2 Nonvolatile Memory: Cross-Point Memories 34
2.3.2.1 Cross-Point Memory Architectures 34
2.3.2.2 Diode/Antifuse Cross-Point Memory: Technology 35
2.3.2.3 Diode/Antifuse Cross-Point Memory: Die Size Considerations 36
2.3.3 Nonvolatile Memory: TFT-SONOS 38
2.4 Non-Silicon Monolithic 3D Integrated Circuits 40
2.5 Summary 41
3 Stacked CMOS Technologies 44
3.1 Stacked Complementary Metal-Oxide Semiconductor Topology 44
3.2 Stacked CMOS Processes and Device Design 46
3.2.1 Layer-by-Layer Process 46
3.2.2 Simultaneous Multilayer Processing 47
3.2.2.1 Gate Definition of Lower Layers 47
3.2.2.2 Doping the Bottom Layer 48
3.2.2.3 Making Contact Between Two Active Layers 49
3.2.3 Layout Issues 50
3.3 Stacked CMOS on the Thin Film and the Substrate of a SOI Wafer 51
3.4 Stacked FinCMOS Technology 54
3.5 Summary 60
4 Wafer-Bonding Technologies and Strategies for 3D ICs 61
4.1 Introduction 61
4.2 Wafer-Bonding Equipment Overview 61
4.3 Surface Preparation Treatments 63
4.3.1 Surface Preparation Treatments -- Wet Chemistry 63
4.3.2 Surface Preparation Treatments -- Plasma Activation 65
4.3.3 Surface Preparation Treatments -- Combined Plasma and Wet Chemistry 66
4.3.4 Surface Preparation Treatments -- Vapor Cleaning 67
4.4 Bond Aligner -- Equipment Working Principle 70
4.5 Alignment Strategies 71
4.6 Wafer Transfer Fixtures 78
4.7 Wafer-Bonding Technology 81
4.7.1 Bond Chamber Design and Components 81
4.8 Wafer-Bonding Techniques for 3D 84
4.8.1 Silicon Direct Bonding 84
4.8.2 BCB Bonding 85
4.8.3 Coppert-to-Copper Diffusion Bonding 87
4.8.4 Eutectic Bonding 90
4.9 Bond Quality Testing 92
4.10 Summary 93
5 Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies 96
5.1 Introduction 96
5.2 Through-Silicon Vias Compared with Wirebonds 96
5.3 Through-Silicon Via Hole Formation 97
5.3.1 TSVs for Die-to-Wafer Stacking: Laser Drilling 98
5.3.2 TSVs for Die-to-Wafer Stacking: Etching 98
5.3.3 TSVs for Wafer-to-Wafer Stacking 100
5.4 Dielectric Liner for TSVs 101
5.5 Tungsten Via Fill and Polish 103
5.5.1 Contact/Seed/CVD Tungsten Depositions 103
5.6 Copper Via Fill 103
5.6.1 Barrier and Seed Layers for Copper Plating 103
5.6.2 Electroplating Copper 105
5.6.3 Chemical--Mechanical Polish (CMP) of Copper 106
5.7 Wafer Thinning 106
5.7.1 Backgrind 106
5.7.2 Wet Etching Silicon to Thin the Wafer and Relieve Stress from Grinding 109
5.7.3 Fracturing Wafers at a Hydrogen Implant-Damaged Plane 109
5.8 Singulation 110
5.9 Handle Wafer Technologies 112
5.9.1 Substrate 113
5.9.2 Bonding Layer 114
5.9.2.1 Bond Strength 114
5.9.2.2 Maximum-Use Temperature 114
5.9.2.3 Chemical Stability 114
5.9.2.4 Vacuum Compatibility 115
5.9.2.5 Final Thickness and Planarity 115
5.9.2.6 Releasibility 115
5.9.3 Optional Release Layer 116
5.10 Wafer-Bonding Methods 116
5.10.1 Thermoplastic Materials 116
5.10.2 UV-Curable Materials 118
5.10.3 Laminates 119
5.10.4 Metal Based 120
5.11 Handle Wafer Use 120
5.12 Wafer Debonding Methods 122
5.12.1 Chemical Methods 122
5.12.2 Thermal Methods 122
5.12.3 Laser Treatment 124
5.13 Post-release Treatments 124
5.14 Summary, Conclusions, and Future Projections 124
6 Cu Wafer Bonding for 3D IC Applications 128
6.1 Introduction 128
6.2 Classification of Cu-Bonding Techniques 128
6.2.1 Surface-Activated Cu Bonding 128
6.2.2 Thermal Compression Cu Bonding 129
6.3 Fundamental Properties of Cu Bonding 129
6.3.1 Morphology of Cu-Bonded Layer 130
6.3.2 Oxide Examination of Cu-Bonded Layer 130
6.3.3 Microstructure Evolution During Cu Bonding 131
6.3.4 Orientation Evolution During Cu Bonding 132
6.4 Cu-Bonding Development 133
6.4.1 Structural Design 133
6.4.2 Copper Pad Fabrication 134
6.4.3 Bond Parameters 134
6.5 Cu Bond Quality Characterization and Alignment Accuracy 135
6.6 Reliable Cu Bonding and Multilayer Stacking 137
6.7 Applications of Cu Wafer Bonding 139
6.8 Summary 140
7 Cu/Sn Solid-Liquid Interdiffusion Bonding 142
7.1 The Principle of Solid--Liquid Interdiffusion 143
7.1.1 Liquefaction and Liquid Phase Properties 144
7.1.1.1 Characteristics of Soldering with Thin Solder Layers 144
7.1.1.2 Hydrostatics of the Solder Pad 146
7.1.2 Metallurgy and Intermetallic Growth 147
7.1.2.1 Phase Front Propagation in Cu/Sn Diffusion Couples 148
7.1.2.2 Calculation of the Metal Pad Thickness 150
7.1.3 Process Conditions and Characteristics 151
7.1.3.1 Surface Metal Oxides 151
7.1.3.2 Parasitic Consumption of Reactive Solder 151
7.1.3.3 Wetting versus Intermetallic Growth 153
7.1.3.4 Electromigration 153
7.2 Chip-Stacking: The SOLID-F2F Process 154
7.2.1 Process Flow 155
7.2.2 Behavior of Underfill in Small Gaps 156
7.2.3 Self-Alignment 158
7.2.4 Reliability Results 158
7.2.4.1 Thermal Cycling 159
7.2.4.2 High-Temperature Storage 159
7.2.4.3 Corrosion 160
7.2.4.4 Electromigration 162
7.3 Three-Dimensional Integration: SLID for Multichip Stacking 163
7.3.1 Scheme with SLID and Backside Vias 164
7.3.1.1 Basic Considerations 164
7.3.1.2 Preprocessing 165
7.3.1.3 Processing 165
7.3.1.4 Stack Building 168
7.3.1.5 Results 169
7.3.2 Scheme with ICV-SLID Technology 170
7.3.2.1 Processes 170
7.3.2.2 Results 172
7.3.3 Scheme with Copper Bump Bonding 172
7.3.3.1 Process Scheme 173
7.3.3.2 CBB Process 173
7.4 Brief Discussion on W2W Versus C2W Schemes 175
7.5 Conclusion 176
8 An SOI-Based 3D Circuit Integration Technology 181
8.1 Introduction 181
8.2 Lincoln Laboratory's Wafer-Scale 3D Circuit Integration Technology 182
8.2.1 Three-Dimensional Fabrication Process 182
8.2.2 Three-Dimensional Enabling Technologies 184
8.2.3 Three-dimensional Technology Scaling 189
8.3 Transferred FDSOI Transistor and Device Properties 191
8.4 Multiproject Circuit Design and Layout in Lincoln Laboratory's 3D Technology 193
8.4.1 Three-Dimensional Design and Layout Practice 194
8.4.2 Computer-Aided Design Tool Refinements 194
8.4.3 Three-Dimensional Design Optimization 195
8.4.4 Wafer--Wafer Alignment Aids 196
8.4.5 Three-Dimensional Design and Submission Procedures 198
8.4.6 Three-Dimensinal Circuit Design Examples 198
8.5 Three-Dimensional Circuit and Device Results 201
8.5.1 Three-Dimensional-LADAR Chip 201
8.5.2 1024 1024 3D Visible Imager 203
8.5.3 Heterogeneous Integration 204
8.6 Summary 204
9 3D Fabrication Options for High-Performance CMOS Technology 207
9.1 3-D Technology 207
9.1.1 Introduction 207
9.1.2 Three-Dimensional Technology Landscape 208
9.1.3 Wafer-Level 3D Integration 209
9.1.4 IBM 3D Integration Approaches 211
9.1.4.1 Copper Bonding with TSVs for Processor/Memory Stacking 211
9.1.4.2 SOI-Based 3D Integration for Ultrahigh-Density and Device-Level Stacking 216
9.2 Future Development Activities for 3D Integration 222
9.2.1 Thermal Dissipation in Bonded Structures 222
9.2.2 Noise in 3D Integrated Structures 223
9.2.3 Bandwidth Utilization and Smart Power-Efficient Designs (Lower-Power Voltage Operations, Energy Efficiency) 223
9.2.3.1 Bandwidth Advantages of 3D 223
9.2.4 Power-Efficient 3D Possibilities 224
9.3 Summary 225
10 3D Integration Based upon Dielectric Adhesive Bonding 228
10.1 Introduction 228
10.2 Adhesive Bonding Mechanisms and Dielectric Adhesives 229
10.2.1 Desired Properties of Polymer Adhesive Materials for Wafer Bonding 230
10.2.2 Adhesive Wafer-Bonding Technology 231
10.3 Wafer-Level 3D Integration Platforms Based upon Adhesive Bonding 234
10.3.1 Via-Last 3D Platform Using Blanket Adhesive Wafer Bonding and Cu Damascene Interstrata Interconnects 236
10.3.2 Via-First 3D Platform with Wafer-Bonding of Damascene-Patterned Metal/Adhesive Redistribution Layers 236
10.4 Impacts of Soft-Baked BCB and Partially Cured BCB 238
10.4.1 Thickness Uniformity of BCB Layers 239
10.4.2 BCB Bond Strength and Impact on Bonding Void and Defects 240
10.4.3 Impact on Wafer-to-Wafer Alignment Accuracy 241
10.5 Integrity Characterizations of Blanket Adhesive Wafer Bonding 242
10.5.1 Optical Inspection Using Glass Wafer 242
10.5.2 Bonding Strength Characterization Using Four-Point Bending 243
10.5.3 Thermal Cycling Test 245
10.5.4 Packaging Reliability Tests 245
10.5.5 Wafer Thinning 246
10.5.6 Electrical Characterization of Adhesive Wafer-Bonding Integrity 247
10.6 Integrity Characterizations of Patterned/Processed Adhesive Wafer Bonding 249
10.6.1 Partially Cured BCB for Copper Damascene Patterning 250
10.6.2 Bond Strength and Voids/Defects 251
10.6.3 Surface Topography of Damascene-Patterned Cu/BCB Layer 251
10.7 Feasibility Demonstrations of Wafer-Level 3D Integration 252
10.7.1 Via-Last 3D Platform Feasibility Demonstration 252
10.7.2 Via-First 3D Platform Feasibility Demonstration 254
10.8 Thermomechanical Modeling 257
10.9 General Discussions on 3D Platforms and Applications 259
10.10 Conclusions 261
11 Direct Hybrid Bonding 266
11.1 Introduction 266
11.2 The Direct Hybrid Bonding Process 268
11.2.1 TSV Die Preparation 268
11.2.2 Preparation of the Landing Surface: Dielectric Application and Patterning 270
11.3 Choice of Metal Bond Type and Dielectric 273
11.4 Collective Hybrid Bonding 274
11.4.1 Requirements for Pick-and-Place 275
11.4.2 Compliant Bonding 275
11.5 Summary 276
12 3D Memory 277
12.1 A Brief History of Memory 277
12.2 3D Memory By Many Means 277
12.2.1 3D Packaging 277
12.2.2 3D ICs 279
12.2.2.1 Separate Fabrication or Sequential Fabrication? 281
12.2.2.2 Wafer Scale or Device Scale? 282
12.3 DRAM 282
12.3.1 DRAM Manufacturing 282
12.3.2 Simplified DRAM Overview 283
12.3.3 DRAM Construction Issues 283
12.3.4 Array Efficiency 286
12.3.5 The Memory Wall 286
12.3.6 Repair and Redundancy, Test, and Reliability 287
12.3.7 3D Benefits in DRAM 289
12.4 Building 3D DRAM 289
12.4.1 Latency 290
12.4.2 Power 291
12.4.3 Reliability 291
12.4.4 Cost 292
12.4.4.1 Memory Wafer Processing 292
12.4.4.2 Array Efficiency 292
12.4.4.3 Testing 293
12.4.4.4 Improved Yield 293
12.4.5 Other Benefits of 3D Memory 294
12.5 Tezzaron 3D Process Flow 294
12.6 Embedded Memory versus Stacked Memory 297
12.7 3D Futures 298
13 Circuit Architectures for 3D Integration 300
13.1 Introduction 300
13.2 Three-Dimensional SOC 301
13.2.1 Parasitic Coupling 302
13.3 Digital Systems 304
13.3.1 Imager Systems 304
13.3.2 Interconnect-Dominated Systems 305
13.4 Nanoscale/Microscale Integration 308
13.5 Comparison Between 3D Integration and Planar Packaging 311
14 Thermal Challenges of 3D ICs 313
14.1 Introduction 313
14.2 Thermal Effects in 3D ICs in the Nanometer Regime 315
14.2.1 Impact of Heat on Device and Interconnect Reliability 315
14.2.2 Analytical Average Die Temperature Model 315
14.2.3 Origin and Significance of Electrothermal Couplings 317
14.3 Self-Consistent Temperature Estimation for 3D ICs 319
14.3.1 Typical Chip Package Structure and Heat Transfer Mechanisms 320
14.3.2 Full-Chip Package Thermal Model 321
14.3.3 Numerical Approach and Methodology Overview 323
14.3.4 Setup and Implementation: An Example of a 2D IC Thermal Profile Estimation 326
14.3.5 3D IC Thermal Profile Estimation: Analysis and Implications 329
14.4 Implications and Opportunities for 3D IC Thermal Management 333
14.5 Summary 335
15 Status and Outlook 339
15.1 Introduction 339
15.2 Technology and Applications 339
15.2.1 System Integration 339
15.2.2 Vertical Interconnect 341
15.2.2.1 Vertical Interconnect Density and Applications 342
15.2.2.2 Interstratum Connections 343
15.2.2.3 Through-Stratum Vias 343
15.2.3 Bonded Vertical Integration Technologies 345
15.2.3.1 Alignment and Bonding 345
15.2.3.2 Stratum Thinning 347
15.2.4 Design 347
15.3 Packaging of 3D Devices 349
15.3.1 Signal, Power, and Ground Congestion 349
15.3.2 Thermal Congestion and Heat Dissipation 350
15.3.3 Reliability of Packaged 3D Devices 350
15.4 Market and Economics of 3D 351
15.4.1 Technology Maturity 351
15.4.2 Cost 351
15.5 Market Projections 354
Index 359
| Erscheint lt. Verlag | 29.6.2009 |
|---|---|
| Reihe/Serie | Integrated Circuits and Systems |
| Zusatzinfo | XII, 410 p. |
| Verlagsort | New York |
| Sprache | englisch |
| Themenwelt | Naturwissenschaften ► Geowissenschaften ► Geografie / Kartografie |
| Technik ► Elektrotechnik / Energietechnik | |
| Technik ► Maschinenbau | |
| Schlagworte | Applications enabled by 3-D integration • Circuit • CMOS • Design • Diffusion • Integrated circuit • Silicon • Technologie • Technology • Three-dimensional (3-D) integration • three dimensional integrated circuit • Through Silicon vias (TSVs) • Wafer • Wafer bonding • Wafer-Level 3-D Technology Platforms |
| ISBN-10 | 0-387-76534-4 / 0387765344 |
| ISBN-13 | 978-0-387-76534-1 / 9780387765341 |
| Haben Sie eine Frage zum Produkt? |
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