Since the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs.
VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools.
This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on Amazon.com have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals.
* Details how the new standard allows for increased portability across tools.
* Covers related standards, including the Numeric Synthesis Package and the Synthesis Operability Package, demonstrating how they can be used for digital systems design.
* Presents four extensive case studies to demonstrate and combine features of the language taught across multiple chapters.
* Requires only a minimal background in programming, making it an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD.
Since the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs. VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools. This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on Amazon.com have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals.* Details how the new standard allows for increased portability across tools.* Covers related standards, including the Numeric Synthesis Package and the Synthesis Operability Package, demonstrating how they can be used for digital systems design.* Presents four extensive case studies to demonstrate and combine features of the language taught across multiple chapters.* Requires only a minimal background in programming, making it an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD.
Front Cover 1
The Designer’s Guide to VHDL 4
Copyright Page 5
Contents 12
Foreword 8
Foreword to the First Edition 10
Preface 26
Chapter 1. Fundamental Concepts 32
Modeling Digital Systems 33
Domains and Levels of Modeling 35
Modeling Languages 38
VHDL Modeling Concepts 39
Learning a New Language: Lexical Elements and Syntax 47
Exercises 57
Chapter 2. Scalar Data Types and Operations 60
Constants and Variables 61
Scalar Types 63
Type Classification 77
Attributes of Scalar Types 80
Expressions and Operators 83
Exercises 85
Chapter 3. Sequential Statements 88
If Statements 89
Case Statements 92
Null Statements 97
Loop Statements 98
Assertion and Report Statements 108
Exercises 114
Chapter 4. Composite Data Types and Operations 116
Arrays 117
Unconstrained Array Types 125
Array Operations and Referencing 129
Records 133
Exercises 136
Chapter 5. Basic Modeling Constructs 138
Entity Declarations 139
Architecture Bodies 141
Behavioral Descriptions 144
Structural Descriptions 171
Design Processing 180
Exercises 188
Chapter 6. Case Study: A Pipelined Multiplier Accumulator 198
Algorithm Outline 199
A Behavioral Model 202
A Register-Transfer-Level Model 210
Exercises 224
Chapter 7. Subprograms 226
Procedures 227
Procedure Parameters 233
Concurrent Procedure Call Statements 244
Functions 246
Overloading 251
Visibility of Declarations 254
Exercises 258
Chapter 8. Packages and Use Clauses 262
Package Declarations 263
Package Bodies 270
Use Clauses 272
The Predefined Package Standard 274
IEEE Standard Packages 275
Exercises 286
Chapter 9. Aliases 288
Aliases for Data Objects 289
Aliases for Non-Data Items 292
Exercises 295
Chapter 10. Case Study: A Bit-Vector Arithmetic Package 298
The Package Interface 299
The Package Body 302
An ALU Using the Arithmetic Package 311
Exercises 313
Chapter 11. Resolved Signals 316
Basic Resolved Signals 317
IEEE Std_Logic_1164 Resolved Subtypes 325
Resolved Signals and Ports 328
Resolved Signal Parameters 331
Exercises 333
Chapter 12. Generic Constants 340
Parameterizing Behavior 341
Parameterizing Structure 344
Exercises 346
Chapter 13. Generic Constants Components and Configurations 348
Components 349
Configuring Component Instances 353
Configuration Specifications 368
Exercises 375
Chapter 14. Generate Statements 380
Generating Iterative Structures 381
Conditionally Generating Structures 386
Configuration of Generate Statements 393
Exercises 398
Chapter 15. Case Study: The DLX Computer System 404
Overview of the DLX CPU 405
A Behavioral Model 413
Testing the Behavioral Model 438
A Register-Transfer-Level Model 447
Testing the Register-Transfer-Level Model 483
Exercises 487
Chapter 16. Guards and Blocks 490
Guarded Signals and Disconnection 491
Blocks and Guarded Signal Assignment 500
Using Blocks for Structural Modularity 506
Exercises 513
Chapter 17. Access Types and Abstract Data Types 518
Access Types 519
Linked Data Structures 525
Abstract Data Types Using Packages 530
Exercises 543
Chapter 18. Files and Input/Output 546
Files 547
The Package Textio 560
Exercises 575
Chapter 19. Case Study: Queuing Networks 580
Queuing Network Concepts 581
Queuing Network Modules 582
A Queuing Network for a Disk System 609
Exercises 615
Chapter 20. Attributes and Groups 616
Predefined Attributes 617
User-Defined Attributes 626
Groups 639
Exercises 642
Chapter 21. Miscellaneous Topics 646
Buffer and Linkage Ports 647
Conversion Functions in Association Lists 649
Postponed Processes 654
Shared Variables 657
Exercises 667
Chapter A. Synthesis 670
Use of Data Types 671
Interpretation of Standard Logic Values 673
Modeling Combinatorial Logic 674
Modeling Sequential Logic 675
VHDL Modeling Restrictions 681
Chapter B. The Predefined Package Standard 686
Chapter C. IEEE Standard Packages 690
Std_Logic_1164 Multivalue Logic System1 690
Standard 1076.3 VHDL Synthesis Packages2 693
Standard 1076.2 VHDL Mathematical Packages3 696
Chapter D. Related Standards 702
IEEE VHDL Standards 702
Other Design Automation Standards 708
Chapter E. VHDL Syntax 714
Design File 716
Library Unit Declarations 716
Declarations and Specifications 717
Type Definitions 720
Concurrent Statements 721
Sequential Statements 723
Interfaces and Associations 724
Expressions 725
Chapter F. Differences among VHDL-87, VHDL-93 and VHDL-2001 728
Lexical Differences 728
Syntactic Differences 729
Semantic Differences 730
Differences in the Standard Environment 731
VHDL-93 Facilities Not in VHDL-87 732
VHDL-2001 Facilities Not in VHDL-87 or VHDL-93 732
Features under Consideration for Removal 732
Chapter G. Answers to Exercises 734
Chapter H. Software Guide 754
Software Overview 754
Installation 755
Example VHDL Code 758
Exploration/VHDL Quick Start Guide 759
Example 760
References 774
Index 776
Preface
VHDL is a language for describing digital electronic systems. It arose out of the United States government’s Very High Speed Integrated Circuits (VHSIC) program. In the course of this program, it became clear that there was a need for a standard language for describing the structure and function of integrated circuits (ICs). Hence the VHSIC Hardware Description Language (VHDL) was developed. It was subsequently developed further under the auspices of the Institute of Electrical and Electronic Engineers (IEEE) and adopted in the form of the IEEE Standard 1076, Standard VHDL Language Reference Manual, in 1987. This first standard version of the language is often referred to as VHDL-87.
Like all IEEE standards, the VHDL standard is subject to review every five years. Comments and suggestions from users of the 1987 standard were analyzed by the IEEE working group responsible for VHDL, and in 1992 a revised version of the standard was proposed. This was eventually adopted in 1993, giving us VHDL-93. A second round of revision of the standard was started in 1998. That process was completed in 2001, giving us the current version of the language, VHDL-2001, described in this book.
VHDL is designed to fill a number of needs in the design process. First, it allows description of the structure of a system, that is, how it is decomposed into subsystems and how those subsystems are interconnected. Second, it allows the specification of the function of a system using familiar programming language forms. Third, as a result, it allows the design of a system to be simulated before being manufactured, so that designers can quickly compare alternatives and test for correctness without the delay and expense of hardware prototyping. Fourth, it allows the detailed structure of a design to be synthesized from a more abstract specification, allowing designers to concentrate on more strategic design decisions and reducing time to market.
This book presents a structured guide to the modeling facilities offered by the VHDL language, showing how they can be used for the design of digital systems. The book does not purport to teach digital design, since that topic is large enough by itself to warrant several textbooks covering its various aspects. Instead, the book assumes that the reader has at least a basic grasp of digital design concepts, such as might be gained from a first course in digital design in an engineering degree program. Some exposure to computer programming and to concepts of computer organization will also be beneficial. This book is suitable for use in an introductory or intermediate-level course in digital or computer design. It will also serve practicing engineers who need to acquire VHDL fluency as part of their changing job requirements.
I am particularly pleased to be able to include this book in the Morgan Kaufmann Series in Systems on Silicon. Modeling for simulation and synthesis is a vital part of a design methodology for large-scale systems. VHDL allows models to be expressed at a range of levels of abstraction, from gate-level up to algorithmic and architectural levels. It will continue to play an important role in the design of silicon-based systems for some time to come.
Structure of the Book
The Designer’s Guide to VHDL is organized so that it can be read linearly from front to back. This path offers a graduated development, with each chapter building on ideas introduced in the preceding chapters. Each chapter introduces a number of related concepts or language facilities and illustrates each one with examples. Scattered throughout the book are four case studies, which bring together preceding material in the form of extended worked examples.
Chapter 1 introduces the idea of a hardware description language and outlines the reasons for its use and the benefits that ensue. It then proceeds to introduce the basic concepts underlying VHDL, so that they can serve as a basis for examples in subsequent chapters. The next three chapters cover the aspects of VHDL that are most like conventional programming languages. These may be used to describe the behavior of a system in algorithmic terms. Chapter 2 explains the basic type system of the language and introduces the scalar data types. Chapter 3 describes the sequential control structures, and Chapter 4 covers composite data structures used to represent collections of data elements.
In Chapter 5, the main facilities of VHDL used for modeling hardware are covered in detail. These include facilities for modeling the basic behavioral elements in a design, the signals that interconnect them and the hierarchical structure of the design. The combination of facilities described in these early chapters is sufficient for many modeling tasks, so Chapter 6 brings them together in the first case study, in which a multiplier/accumulator circuit is designed.
The next group of chapters extends this basic set of facilities with language features that make modeling of large systems more tractable. Chapter 7 introduces procedures and functions, which can be used to encapsulate behavioral aspects of a design. Chapter 8 introduces the package as a means of collecting together related parts of a design or of creating modules that can be reused in a number of designs. It also describes a number of packages standardized by the IEEE for use in VHDL designs. Chapter 9 then covers aliases as a way of managing the large number of names that arise in a large model. The material in this group of chapters is brought together in the next case study in Chapter 10, in which a package of binary arithmetic operations is developed.
The third group of chapters covers advanced modeling features in VHDL. Chapter 11 deals with the important topic of resolved signals, and Chapter 12 describes generic constants as a means of parameterizing the behavior and structure of a design. While these language facilities form the basis of many real-world models, their treatment in this book is left to this late chapter. Experience has shown that the ideas can be difficult to understand without a solid foundation in the more basic language aspects. Chapter 13 deals with the topics of component instantiation and configuration. These features are also important in large real-world models, but they can be difficult to understand. Hence this book introduces structural modeling through the mechanism of direct instantiation in earlier chapters and leaves the more general case of component instantiation and configuration until this later chapter. In Chapter 14, generated regular structures are covered. Chapter 15 brings the material in this group of chapters together in the third case study, in which a register-transfer-level model of a CPU is described.
The fourth group of chapters covers language facilities generally used for system-level modeling. Chapter 16 is a detailed treatment of the related topics of guarded signals and blocks. Chapter 17 introduces the notion of access types (or pointers) and uses them to develop linked data structures. This leads to a discussion of abstract data types as a means of managing the complexity associated with linked data structures. Chapter 18 covers the language facilities for input and output using files, including binary files and text files. Chapter 19 is a case study in which a queuing network model of a computer system is developed.
The final pair of chapters draws the tour of VHDL to a close by covering the remaining language facilities. Chapter 20 describes the attribute mechanism as a means of annotating a design with additional information. Chapter 21 is a miscellany of advanced topics not covered in the previous chapters.
Whereas a complete reading of this book provides a complete coverage of the language, there are several shorter paths through the material. Some suggested minimal paths for readers with different requirements are as follows.
Each chapter in the book is followed by a set of exercises designed to help the reader develop understanding of the material. Where an exercise relates to a particular topic described in the chapter, the section number is included in square brackets. An approximate “difficulty” rating is also provided, expressed using the following symbols:
quiz-style exercise, testing basic understanding
basic modeling exercise—–10 minutes to half an hour effort
advanced modeling exercise—one half to two hours effort
modeling project—half a day or more effort
Answers for the first category of exercises are provided in Appendix G. The remaining categories involve developing VHDL models. Readers are encouraged to test correctness of their models by running them on a VHDL simulator. This is a much more effective learning exercise than comparing paper models with paper solutions.
One pervasive theme running through...
| Erscheint lt. Verlag | 5.6.2001 |
|---|---|
| Sprache | englisch |
| Themenwelt | Mathematik / Informatik ► Informatik ► Netzwerke |
| Mathematik / Informatik ► Informatik ► Programmiersprachen / -werkzeuge | |
| Mathematik / Informatik ► Informatik ► Theorie / Studium | |
| Technik ► Elektrotechnik / Energietechnik | |
| ISBN-10 | 0-08-047715-1 / 0080477151 |
| ISBN-13 | 978-0-08-047715-2 / 9780080477152 |
| Haben Sie eine Frage zum Produkt? |
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