VHDL Coding and Logic Synthesis with Synopsys (eBook)

Cover 1
Table of Contents 8
List of Figures 12
List of Tables 16
List of Examples 18
Preface 20
Acknowledgment 24
Trademarks 25
Part I: VHDL CODING 26
Chapter 1. Introduction 28
1.1 Conventional Design„Schematic Capture 28
1.2 Hardware Description Language 29
1.3 VHDL Design Structure 29
1.4 Component Instantiation Within a VHDL Design Structure 33
1.5 Structural, Behavioral, and Synthesizable VHDL Design Structure 35
1.6 Usage of Library Declarations in VHDL Design Structure 42
Chapter 2. VHDL Simulation and Synthesis Flow 44
Chapter 3. Synthesizable Code for Basic Logic Components 46
3.1 AND Logic 46
3.2 OR Logic 47
3.3 NOT Logic 49
3.4 NAND Logic 49
3.5 NOR Logic 51
3.6 Tristate Buffer Logic 52
3.7 Complex Logic Gate 53
3.8 Latch 54
3.9 Flip-Flop 58
3.10 Decoder 59
3.11 Encoder 61
3.12 Multiplexer 63
3.13 Priority Encoder 64
3.14 Memory Cell 67
3.15 Adder 68
3.16 Component Inference 70
Chapter 4. SignaI Versus Variable 72
4.1 Variable 72
4.2 Signal 73
4.3 When to Use Signal and When to Use Variable 77
4.4 Usage of Loopback Signal 78
Chapter 5. Examples of Complex Synthesizable Code 82
5.1 Shifter 82
5.2 Counter 92
5.3 Memory Module 98
5.4 Car Traffic Controller 106
Chapter 6. Pipeline Microcontroller Synthesizable Design 112
6.1 Instruction Set Definition 112
6.2 Architectural Definition 113
6.3 Pipeline Definition 116
6.4 Microarchitecture Definition for the Pipeline Microcontroller 117
Part II: LOGIC SYNTHESIS WITH SYNOPSYS 170
Chapter 7. Timing Considerations in Design 172
7.1 Setup Timing Violation 172
7.2 Hold Timing Violation 173
7.3 Setup/Hold Timing Considerations in Synthesis 174
7.4 Microarchitectural Tweaks for Fixing Setup Time Violations 175
7.5 Microarchitectural Tweaks for Fixing Hold Time Violations 179
7.6 Asynchronous/False Paths 180
7.7 Multicycle Paths 180
Chapter 8. VHDL Synthesis with Timing Constraints 182
8.1 Introduction to Design Compiler 182
8.2 Using Design Compiler for Synthesis 183
8.3 Performance Tweaks 186
8.4 Area Optimization in Synthesis Tweaks 217
8.5 Fixing Hold-Time Violations in Synopsys 220
8.6 Misc Synthesis Commands Generally Used 220
8.7 Top-Down and Bottoms-Up Compilation 250
Chapter 9. GTECH Instantiation 254
Chapter 10. DesignWare Library 256
10.1 Creating Your Own DesignWare Library 260
Chapter 11. Testability Issues in Synthesis 268
11.1 Multiplexed Flip-Flop Scan Style 269
11.2 Using Synopsys Test Compiler for Scan Insertion 271
Chapter 12. FPGA Synthesis 278
Chapter 13. Synthesis Links to Layout 288
13.1 Forward-Annotation 288
13.2 Wireload Models 289
13.3 Floorplanning a Design 291
13.4 Post Layout Optimization 292
Chapter 14. Design Guideline to Follow for Efficient Synthesis 294
Appendix A. (STD_LOGIC_1164 Library) 296
Appendix B. (Shifter Synthesis Results) 328
Appendix C. (Counter Synthesis Results) 334
Appendix D. (Pipeline Microcontroller Synthesis Results„Top-Down Compilation) 338
Appendix E. (EDIF File of Synthesized Microcontroller Example from Chapter 6) 354
Appendix F. (SDF File from Synthesized Microcontroller Example of Chapter 6) 380
Glossary 410
Bibliography 412
Index 414