Materials for Advanced Packaging (eBook)

Dr. Daniel Lu is the Vice President of Technology, Henkel Corporation in Asia Pacific. Prior to joining Henkel, he worked for the R&D department of Intel Corp (Arizona, USA) as a Sr. Scientist for 7 years. He received his MS and PhD degrees on Polymer Science and Engineering from Georgia Institute of Technology in 1996 and 2000, respectively. Dr. Lu received many awards including the IEEE/CPMT Outstanding Young Engineer Award in 2004, the IEEE ECTC best poster paper in 2007, Intel’s most patent filing in 2003-2007, etc. Dr. Lu has published more than 50 journal papers, wrote chapters for six books, and holds more than 80 US and international patents. He is the editor of the book “Materials for Advanced Packaging (2008)” and co-author of the book “Electronically Conductive Adhesives with Nanotechnologies (2009)”. He has been serving key roles in organizing international electronic packaging conferences and teaching professional development courses in these conferences. Dr. Lu is a senior member of IEEE, and an associate editor of IEEE Transactions on Advanced Packaging and Journal of Nanomaterials, and an editorial board member of Nanoscience & Nanotechnology-Asia. Dr. Lu also serves as an adjunct professor in Huazhong University of Science and Technology, and SIAT (Shenzhen Institute of Advanced Technologies), Chinese Academy of Science. Dr. Lu has more 15 years of experience in electronic packaging and is an expert in electronic packaging materials and processing.Professor C.P. Wong is with the School of Materials Sciences and Engineering at Georgia Tech (GT) and also is the Dean of Engineering, The Chinese University of Hong Kong. Prior to joining GT, he was with AT&T Bell Laboratories for many years and was an AT&T Bell Labs Fellow. His research interests focus on the areas of material and process for electronic, photonic, MEMS, sensors, and energy harvesting and storage. He has published over 1,000 technical papers, 12 books and holds over 65 US Patents. He is a member of the US National Academy of Engineering and a Foreign Academician of the Chinese Academy of Engineering.

Preface 5
Preface to the First Edition 7
Contents 9
Contributors 11
About the Authors 15
Chapter 1: 3D Integration Technologies: An Overview 17
1.1 Introduction 17
1.1.1 Motivation for 3D Integration 18
1.1.2 Technology Platforms for 3D Integration and Packaging 19
1.2 Major Key Enabling 3D Technologies and Materials 20
1.2.1 Typical 3D Integration Process Flows 21
1.2.2 Wafer Thinning and Dicing 21
1.2.3 Wafer and Chip Stacking 24
1.3 TSV Integration Scheme and Process 25
1.3.1 TSV Integration Scheme and Process 26
1.3.1.1 TSV Integration Scheme 26
1.3.1.2 TSV Process Flow 26
1.3.1.3 TSV Scaling 28
1.3.2 Alternative TSV Process Options 28
1.4 Potential Limitations to 3D System Integration 32
1.5 Major Applications of 3D Integration 33
1.6 3D Integration Perspectives 37
References 39
Chapter 2: Advanced Bonding/Joining Techniques 43
2.1 Adhesive Bonding Techniques 44
2.1.1 Adhesives in the Electronic Industries 44
2.1.1.1 Epoxy Resins 44
2.1.1.2 Silicone Resins 44
2.1.1.3 Polyimides 45
2.1.1.4 Acrylics 45
2.1.2 Applications of Adhesives in Electronics 45
2.1.2.1 Integrated Circuits 45
2.1.2.2 Flexible Circuit 46
2.1.2.3 Liquid Crystal Display 46
2.1.3 New Adhesives 47
2.1.3.1 Liquid Crystal Polymer (LCP) 47
2.1.3.2 SU 8 Adhesive Bonding 47
2.2 Lead-Free Soldering Processes 48
2.2.1 Basic Soldering Processes 48
2.2.2 The Fluxless Processes Dealing with Tin Oxides 50
2.2.3 Oxidation-Free Fluxless Soldering Technology 51
2.3 Bonding Processes Using Silver Indium System for High Temperature Applications 58
2.3.1 Silver-Indium Phase Diagram and Reactions at 180C 58
2.3.2 Si Chips Bonded to Ag/Cu Substrates Using Ag-In System 59
2.3.3 Bonding Silicon Chips to Aluminum Substrates Using Ag-In System Without Flux 60
2.3.4 The Strength of High Temperature Ag-In Joints Made Between Copper by Fluxless Low Temperature Processes 68
2.3.5 Thermal Cycling Reliability Study of Ag-In Joints Between Si Chips and Cu Substrates Made by Fluxless Processes 75
2.4 Solid-State Bonding Technology 81
2.4.1 Introduction to Solid-State Bonding 81
2.4.2 Fundamental Principle of Solid-State Bonding 81
2.4.3 The Quantum Solid-State Bonding Theory 83
2.4.4 Novel Ag-to-Cu Solid-State Bonding a.k.a Direct Bonding 88
2.4.5 Cu-to-Ag/Cu Solid-State Bonding 89
2.5 Silver Flip-Chip Interconnect Technology 91
2.5.1 10mum Silver Flip-Chip Joints Made by 250C Solid-State Bonding Process 96
References 103
Chapter 3: Advanced Chip-to-Substrate Connections 107
3.1 Introduction 107
3.1.1 ITRS Projections for Flip-Chip Connections 109
3.1.2 Electrical Modeling of I/O 110
3.1.2.1 Parasitic Inductance of Chip-to-Substrate I/O 110
3.1.2.2 Parasitic I/O Capacitance 113
3.1.2.3 Characteristic Impedance 114
3.1.3 Mechanical Modeling 115
3.2 Compliant Solder-Based I/O Structures 118
3.2.1 Peripheral-to-Flip-Chip Area Array Structures 118
3.2.2 Redistribution Using Area Array Solder I/O 119
3.3 Wafer-Scale Compliant I/O 119
3.4 Improved Mechanical Performance Solder-Capped Structures 123
3.5 Solder-Free Chip-to-Substrate Interconnects 126
3.5.1 Copper Interconnects 127
3.5.1.1 Thermal-Compression Bonding 128
3.5.1.2 Surface-Activated Bonding 130
3.5.1.3 All-Copper Chip-to-Substrate Pillar Interconnects 132
3.5.2 Electroplated Copper Column Arrays 133
3.5.3 Compliant Gold Bump Interconnects 135
3.5.4 Electroless NiB Interconnects 136
3.6 Future Needs and Solutions for Chip-to-Substrate Connections 138
3.6.1 Ultra-High Off-Chip Frequency and High Bandwidth Operation 138
3.6.1.1 Coaxial Interconnects 138
3.6.1.2 Electrical and Optical Interconnects 138
3.6.2 Microfluidic Interconnects for Thermal Management 140
References 142
Chapter 4: Advanced Wire Bonding Technology: Materials, Methods, and Testing 146
4.1 Introduction 146
4.2 Interconnection Requirements 150
4.3 Bonding Principles 154
4.3.1 Wire Bonding Types 154
4.3.2 Thermocompression Bonding 156
4.3.3 Ultrasonic Bonding 159
4.3.4 Thermosonic Bonding 159
4.3.5 Other Techniques 161
4.3.6 Machine Optimization 162
4.4 Copper Ball Bonding 164
4.5 Materials 165
4.5.1 Bonding Wire 165
4.5.2 Bond Pads 170
4.5.3 Gold Plating 173
4.5.3.1 Electroplated Gold 173
4.5.3.2 Electroless Autocatalytic Gold 173
4.5.4 Pad Cleaning 174
4.6 Testing 177
4.7 Quality Assurance 184
4.8 Reliability 186
4.8.1 Intermetallics 186
4.8.2 Cratering 187
4.9 Design (Wire Spacing, Loop Height) 190
4.10 Advanced Concepts 193
4.10.1 Fine Pitch 193
4.10.2 Soft Substrates 195
4.10.3 Higher Frequency Bonding 198
4.10.4 Stud Bumping 203
4.10.5 Extreme Temperature Environments 203
4.11 Summary 209
References 209
Chapter 5: Lead-Free Soldering 214
5.1 Main Stream Lead-Free Soldering Practice 214
5.1.1 Driver of Lead-Free Soldering 214
5.1.2 Prevailing Lead-Free Solder Alloys 216
5.1.3 Lead-Free Surface Finishes 217
5.2 Physical and Mechanical Properties of Solder Joints 217
5.2.1 Melting Behavior 217
5.2.2 Creep Behavior 219
5.3 Intermetallic Compounds (IMC) 221
5.3.1 Effect of IMC on Joint Strength 222
5.3.2 Effect of Cu Content in Solder Alloy on IMC Stability on Ni Metallization 222
5.3.3 Effect of Additives on IMC 225
5.3.4 Effect of Metallization and Alloy on IMC 227
5.3.5 Effect of Heat History on IMC 228
5.4 Microstructure Evolution 229
5.4.1 Grain Coarsening 229
5.4.2 Creep-Fatigue 230
5.5 Temperature Cycling Reliability 230
5.5.1 Effect of Cycling Condition and Alloy on Reliability 230
5.5.2 Effect of PCB Metallization on Reliability 231
5.5.3 Effect of Ag Content on Reliability 232
5.6 Fragility 234
5.6.1 Effect of Ag Content on Fragility 234
5.6.2 Effect of Dopant on Fragility 235
5.6.3 Effect of Thermal Cycling Aging and Metallization on Fragility 237
5.7 Electromigration 237
5.8 Tin Whisker 240
5.8.1 Tin Whisker Growth Mechanism 241
5.8.2 Effect of CTE Mismatch on Tin Whisker 242
5.8.3 Effect of CuSn IMC on Tin Whisker 242
5.8.4 Other Means of Alleviating Tin Whisker Formation 243
5.9 Trends and Status of Novel Lead-Free Solder Alloys 243
5.9.1 Low Temperature Solder Alloys 243
5.9.2 Low Cost High Reliability Solder Alloys 244
5.9.3 High Temperature High Reliability Solder Alloys 246
5.10 Summary 246
References 248
Chapter 6: Thin Die Fabrication and Applications to Wafer Level System Integration 252
6.1 Introduction 252
6.2 Temporary Bonding/De-bonding and Thin Wafer Handling 253
6.3 Wafer Thinning 256
6.3.1 Motivation for Wafer Thinning 256
6.3.2 Wafer Thinning Processes, Tools, and Associated Defects 258
6.3.2.1 Mechanical Thinning 258
General Processes 258
Backgrinding Tools, Mechanism, and Defects 259
6.3.2.2 Chemical Mechanical Polishing (CMP) 266
General Processes 266
6.3.2.3 Wet Etching 271
HNA as an Etchant 271
TMAH as an Etchant 274
6.3.2.4 Dry Etching 275
Si Etching by SF6/O2 Plasma 275
Other Plasma and Dry Silicon Etching Processes 277
Plasma Etching Key Performance Parameters and Defectivity 278
6.4 TSV Revealing, Backside Processes, and Dicing 280
6.4.1 TSV Revealing 280
6.4.2 Backside RDL and Bumping 283
6.4.3 Dicing and Isolation 286
6.4.3.1 Blade Dicing 286
6.4.3.2 Laser Ablation 288
6.4.3.3 Stealth Dicing by Laser 292
6.5 Thin Dies for Wafer Level System Integration 293
6.5.1 Integrated Fan-Out Wafer Level System Integration, InFO 294
6.5.2 Chip-on-Wafer-on-Substrate, CoWoS 296
6.5.3 Summary on WLSI 297
References 298
Chapter 7: Advanced Substrates: A Materials and Processing Perspective 301
7.1 Introduction 301
7.1.1 A Brief History: from PCBs to Substrates 306
7.2 Ceramic Substrates 308
7.3 Organic Substrates 308
7.3.1 2L PBGA Substrates 310
7.3.2 4L PBGA Substrates 313
7.3.3 6L PBGA Substrates 314
7.3.4 High Density Interconnect Substrates: HDI 316
7.3.4.1 2L Via in Pad (ViP) Substrates (2L HDI) 316
7.3.4.2 1+2+1 Substrates (4L HDI) 317
7.3.4.3 1+4+1 Substrates (6L HDI) 318
7.3.4.4 2+2+2 Substrates (6L HDI) 318
7.3.5 Single-Sided Substrates 319
7.3.6 Embedded Trace Substrates 319
7.3.7 Substrate-Less Packages Based on Substrate Technology 321
7.3.8 Coreless Substrates 323
7.4 Tape Ball Grid Array: TBGA 325
7.5 PBGA Substrate Trends 325
7.5.1 Low Cost Dielectrics 325
7.5.2 Low Cost Solder Masks 326
7.5.3 Thin Substrates, Thin Dielectrics 326
7.5.4 Low Expansion Dielectrics 327
7.5.5 Surface Finishes 328
7.5.5.1 Electroplated Nickel Gold 328
7.5.5.2 OSP and AFOP 328
7.5.5.3 ENEPIG and EPIG 329
Tin-Based Surface Finishes 329
Immersion Tin: iT 330
Electroplated Tin: eT and Binary Solders 330
Super Juffit 330
7.6 FCBGA Substrates 332
7.7 Specialty Substrates 335
7.7.1 RF Modules 336
7.7.2 High Performance Substrates with Low Dielectric Constant 336
7.7.3 Substrates with Embedded Components 337
7.7.3.1 Buried Passives Substrates 338
7.7.3.2 Embedded Die and Embedded Passives Substrates 338
7.7.3.3 Cavity Substrates 341
References 342
Trademarks 343
Chapter 8: Flip-Chip Underfill: Materials, Process, and Reliability 344
8.1 Introduction 344
8.2 Conventional Underfill Materials and Process 347
8.3 Reliability of Flip-Chip Underfill Packages 350
8.4 New Challenges to Underfill 353
8.5 No-Flow Underfill (NUF) 356
8.5.1 Approaches of Incorporating Silica Fillers into No-Flow Underfill 360
8.6 Molded Underfill 363
8.7 Wafer Level Underfill 366
8.8 Underfill for 3D Stacks 372
8.9 Nanocomposites Underfill 375
8.10 Summary 377
References 379
Chapter 9: New Development Trend of Epoxy Molding Compound for Encapsulating Semiconductor Chips 385
9.1 Introduction 385
9.2 Introduction to Epoxy Molding Compounds 388
9.2.1 Epoxy Resin 389
9.2.2 Hardener 389
9.2.3 Inorganic Filler 390
9.2.4 Silane-Coupling Agent 391
9.2.5 Flame Retardant 392
9.2.6 Other Additives 392
9.3 Beyond Transfer Molding 393
9.3.1 Granule Epoxy Molding Compound 393
9.3.2 Sheet Epoxy Molding Compound 397
9.4 Epoxy Molding Compound for Advanced Packages 399
9.4.1 Flip Chip Application 399
9.4.1.1 Filling Performance 399
9.4.1.2 Warpage Management 401
9.4.1.3 Bump Protection for SiP Application 403
9.4.2 Cu/Ag-Wire Application 404
9.4.2.1 Analysis of Wire Bonding Part After HAST 404
9.4.2.2 Corrosion Mechanism of Wire Bonds 407
9.4.2.3 HTSL Results for EMC 409
9.4.3 Development of EMCs for Premold L/F and Molded Substrate 410
9.4.3.1 Pre-mold L/F 410
9.4.3.2 Molded Substrate 412
9.4.4 WLP Application 415
9.4.4.1 EMC for FOWLP 415
9.4.5 High Temperature Application 420
9.4.5.1 Introduction 420
9.4.5.2 EMC Materials with High Heat Resistance 421
9.4.6 Study of Epoxy Molding Compound for Fingerprint Sensor 425
9.4.6.1 Introduction 425
9.4.6.2 Type of Fingerprint Sensor 426
9.4.6.3 Principle of Fingerprint Sensor 427
9.4.6.4 EMC for Fingerprint Sensor 428
9.5 Summary 430
References 430
Chapter 10: Electrically Conductive Adhesives (ECAs) 432
10.1 Introduction 432
10.2 Description of Anisotropically Conductive Adhesives 432
10.2.1 Overview 432
10.2.2 Adhesive Matrix 433
10.2.3 Conductive Fillers 434
10.2.3.1 Solid Metal Particles 434
10.2.3.2 Non-Metal Particles with Metal Coating 434
10.2.3.3 Metal Particles with Insulating Coating 434
10.2.3.4 Nanoparticles 435
10.2.3.5 Self-Aligned Magnetic Particles 436
10.2.3.6 Nanofiber/Solder 436
10.3 Flip Chip Applications Using Anisotropically Conductive Adhesives 436
10.3.1 ACA Flip Chip for Bumped Dies 437
10.3.1.1 Two Filler Systems 437
10.3.1.2 Coated Plastic Filler 437
10.3.1.3 Solder Filler Systems 438
10.3.1.4 Ni Filler 439
10.3.2 ACA Bumped Flip Chips on Glass Chip Carriers 440
10.3.2.1 Selective Tacky Adhesive Method 440
10.3.2.2 The MAPLE Method 441
10.3.3 ACA Bumped Flip Chips for High Frequency Applications 441
10.3.4 ACA for Unbumped Flip Chips 442
10.3.4.1 Gold-Coated Nickel Filler 442
10.3.4.2 Ni/Au-Coated Silver Filler 443
10.3.4.3 Metal Pillar ACF 443
10.3.5 ACAs for CSP and BGA Applications 444
10.3.5.1 Double-Layered ACF Film 444
10.3.5.2 Ceramic Chip Carriers vs. Organic Chip Carriers 445
10.3.6 Failure Mechanism 445
10.3.6.1 Oxidation of Non-Noble Metals 445
10.3.6.2 Loss of Compressive Force 446
10.4 Description of Isotropic Conductive Adhesives (ICAS) 446
10.4.1 Percolation Theory of Conduction 446
10.4.2 Adhesive Matrix 447
10.4.3 Conductive Fillers 447
10.4.3.1 Silver Particles 448
10.4.3.2 Silver-Coated Copper Particles 448
10.4.3.3 Low-Melt Fillers 448
10.4.3.4 Nanoparticles 449
Silver Nanowires 449
Carbon Nanotubes (CNTs) 449
Copper Nanoparticles 450
AgNPs/Reduced Graphene Oxide (rGO) 450
In Situ NanoAg-Coated Silver Flakes 451
10.5 Flip Chip Applications Using Isotropic Conductive Adhesives 451
10.5.1 Polymer Bump Flip Chip 452
10.5.2 Metal-Bumped Flip Chip Joints 452
10.5.3 ICA Process for Unbumped Chips 453
10.6 Surface Mount Applications 454
10.7 ICAs for CSP Applications 455
10.8 ICAs for Advanced Packaging Applications 456
10.8.1 Solar Cell 456
10.8.2 3D Stacking 456
10.8.3 Microspring 458
10.8.4 ICAs for Printed Circuit Board Applications 459
10.9 High-Frequency Performance of ICA Joints 461
10.10 Reliability of ICA Joints 462
10.11 Recent Advances on ICAS 464
10.11.1 Improvement of Electrical Conductivity 464
10.11.2 Eliminate Lubrication Layer 465
10.11.3 Increase Shrinkage 465
10.11.4 Transient Liquid Phase Fillers 465
10.11.4.1 Incorporation of Intrinsic Conducting Polymers 466
10.11.4.2 Polymer Resin Alloy 466
10.11.5 Improvement of Contact Resistance Stability 467
10.11.5.1 Causes for Resistance Increase 467
10.11.5.2 Approaches to Stabilize Contact Resistance 467
Reduce Moisture Absorption 467
Use of Corrosion Inhibitors 468
Use of Oxygen Scavengers 469
Sharp-Edge Filler Particles 469
10.11.6 Improvement of Impact Performance 470
References 472
Chapter 11: Die Attach Adhesives and Films 480
11.1 Die Attach Materials 480
11.1.1 Trends in Electronic Packaging 480
11.1.2 Trends in Die Attach Materials 482
11.1.3 Demands on Die Attach Materials 484
11.1.4 Die Attach Paste 485
11.1.5 Adhesive Tape for LOC Package 486
11.1.6 Die Attach Film 487
11.1.7 The Future of Advanced Die Attach Film 488
11.1.7.1 Die Attach Film for Advanced BGA/CSP 488
11.1.7.2 Dicing/Die Attach Dual Functioning Film 489
11.1.7.3 Die Attach Film for Multi-Layered Packaging Process 489
11.2 Development of Die Attach Film with High Performance for Package Cracking Resistance and Advanced Package 492
11.2.1 Introduction 493
11.2.1.1 Technical Issues of Silver Paste 493
11.2.1.2 Package Crack 493
11.2.1.3 Advanced Packages 495
11.2.2 Design of Base Resin for Die Attach Film 495
11.2.3 Die Attach Film for Package Crack Resistance 497
11.2.3.1 Water Absorption of Base Resin 497
11.2.3.2 Peel Strength 497
11.2.3.3 Package Cracking Resistance 501
11.2.4 Die Attach Film for Advanced Package 502
11.2.4.1 Low Tg and Low Water Absorptivity of Polyimide Base Resin 502
11.2.4.2 Low Stress (Silicon Chip Warpage) 505
11.2.4.3 Low Attaching Temperature 507
11.2.4.4 Properties of Die Attach Film 508
11.3 Development of Die-Bonding Film by Nano-Structure Control and Mathematical Optimization 510
11.3.1 Material System Based on Reaction-Induced Phase Decomposition 510
11.3.2 Material Design System Based on Reaction-Induced Phase Decomposition 512
11.4 Technologies for Next-Generation Packages 517
References 519
Chapter 12: Thermal Interface Materials 522
12.1 What Is Thermal Interface Resistance? 523
12.2 Recent Development in Thermal Interface Modeling 526
12.2.1 Model to Predict Thermal Conductivity (kTIM) 528
12.2.2 Rheological Model to Predict TIM Bondline Thickness (BLT) 529
12.2.3 Effect of Particle Volume Fraction on Bulk TIM Thermal Resistance 531
12.2.4 Model to Predict Thermal Contact Resistance (Rc) 533
12.3 Reliability Consideration for Polymeric TIMs 535
12.4 Solder Alloy-Based TIMs 537
12.5 Nanotechnology-Based TIMs 538
12.6 Characterization of TIM Thermal Performance 541
12.7 Future Directions 542
References 542
Chapter 13: Embedded Passives 547
13.1 Introduction 547
13.1.1 Passives in Power Modules 547
13.2 Embedded Inductors 551
13.2.1 Introduction 551
13.2.1.1 Limitations of Discrete Inductors and Air Core Spiral Inductors 551
13.2.1.2 Advantages of Magnetic Inductors as Embedded Inductors 552
13.2.1.3 Inductor Designs 553
13.2.1.4 Requirements and Survey for the Magnetic Core Materials 554
13.2.2 Modeling and Design Considerations of Magnetic Inductors 555
13.2.2.1 Inductance 556
13.2.2.2 Resistance 558
13.2.2.3 Quality Factor 560
13.2.2.4 Saturation Current 560
13.2.3 Embedded On-package and On-chip Inductors: Experiments and Analyses 561
13.2.3.1 On-chip Inductor Results 561
13.2.3.2 On-package Inductor Results 563
13.2.3.3 Fundamental Trade-Offs of Magnetic Inductors 565
13.2.4 Future Directions of the Embedded Magnetic Inductors 566
13.2.4.1 Potential Applications for the Integrated Magnetic Inductors 566
13.2.4.2 Survey of Inductor Works in Literature 567
13.2.4.3 Challenges 567
13.2.4.4 Direction for Embedded Inductors 569
13.3 Capacitor Technologies 570
13.3.1 Discrete Capacitors 570
13.3.1.1 MLCC 571
13.3.1.2 Electrolytic Capacitors with Sintered Porous Ta and Etched Al Foils 573
13.3.2 Integrated Capacitors 576
13.3.2.1 Thin-Film Capacitors 576
13.3.2.2 Trench Capacitors 577
13.3.3 Emerging Nanoscale Capacitors 578
13.3.4 Future of Power Capacitors 581
13.4 Embedded Resistors 581
13.4.1 Introduction 581
13.4.2 Fundamental of Resistors 582
13.4.3 Design, Materials, and Processing Technologies 584
13.4.3.1 Design 584
13.4.3.2 Materials and Processes 585
13.4.4 Challenges and Solutions with Embedded Resistors 589
13.4.4.1 Yield 589
13.4.4.2 High Temperature and Humidity Stability 589
13.4.4.3 Precision Patterning with Laser Trimming 590
13.4.4.4 Precision Patterning with Dry Etching 590
13.5 Conclusions 591
References 592
Chapter 14: Advanced Bonding Technology Based on Nano- and Micro-metal Pastes 599
14.1 Introduction 600
14.2 Silver Pastes 602
14.2.1 From Micro-Ag Paste to Nano-Ag Pastes 602
14.2.2 Performance of Joints Based on Nano-Ag Pastes 603
14.2.2.1 Sintering Pressure in Nano-Ag Pastes 604
14.2.2.2 Sintering Temperature and Time in Nano-Ag Pastes 605
14.2.2.3 Heating Rate in Nano-Ag Pastes 606
14.2.3 From Nano-Ag Pastes to Hybrid Silver Pastes 607
14.2.3.1 The Fabrication Methods of Hybrid Ag Pastes 609
14.2.3.2 The Joint Performance and Reliability of Hybrid Ag Pastes 611
14.3 Copper Pastes 615
14.3.1 Synthesis of Cu Pastes 616
14.3.2 Anti-oxidation Methods for the Sintering of Cu Pastes 617
14.3.3 The Joint Performance of Cu Pastes 622
14.4 Other Bonding Techniques 627
14.5 Conclusion 627
References 628
Chapter 15: Wafer Level Chip Scale Packaging 637
15.1 Introduction 637
15.2 Definition of Wafer Level Chip Size Packaging 638
15.3 Materials and Processes for Bumping and Redistribution Technology 642
15.3.1 Metals for Wafer Bumping 642
15.3.1.1 Under Bump Metallization 643
15.3.1.2 Bumping Technologies 644
15.3.1.3 Bump Metallurgy 654
15.3.1.4 Plating of Alloys 659
15.3.1.5 Yield and Reliability 664
15.3.2 Photoresists for Wafer Bumping 665
15.3.3 Processing of Photoresist and Photopolymers 669
15.3.4 Polymers for Redistribution Layers (RDL) 674
15.3.4.1 Chemistry of Polymers for RDL 684
15.3.4.2 Adhesion and Copper Diffusion into Polymers 689
15.4 Materials for Integrated Passives into WLP 694
15.5 Influence of the Polymer to the Reliability of WLP 698
15.6 Conclusion 701
References 702
Chapter 16: Microelectromechanical Systems and Packaging 706
16.1 Introduction 706
16.2 Packaging of MEMS 709
16.3 MEMS for Packaging 719
16.4 Packaging for MEMS 724
16.5 Opportunities and Major Challenges 729
16.6 Conclusions 735
References 736
Chapter 17: LED Die Bonding 741
17.1 LED Chips and Packaging 741
17.1.1 Introduction 741
17.1.2 LED Chips 742
17.1.3 Packages and Packaging 743
17.1.4 Packaging Materials 744
17.2 Die Bonding Materials 744
17.2.1 Material Requirement 745
17.2.2 Types of Die Bonding Materials 746
17.2.2.1 Adhesives 746
Silver DAAs 747
Optical DAAs for Low- and Mid-Power LEDs 747
Optical DAAs for High-Power LEDs 752
17.2.2.2 Adhesive Films 756
17.2.2.3 Solder Materials for LED Die Bonding 757
17.2.2.4 Low-Temperature Sintering Silver Pastes 757
17.3 Packaging and Die Bonding Materials 759
17.3.1 SMD LEDs 759
17.3.1.1 Optical Role of DAAs for Low- and Mid-Power LEDs 760
17.3.1.2 Nonuniformity in SMD LEDs 762
Materials Parameters 763
Process Parameters 763
Package Parameters 766
17.3.1.3 Optimal SMD LEDs Design 767
Guidance of OC-DAAs and WDAAs Design 767
Optimal Selection of Packages 768
Optimal Packaging Processes and Parameters 768
17.3.2 COB LEDs 768
17.3.3 FC LEDs and CSP 770
17.3.4 Wafer-Level CSP LEDs 771
References 772
Chapter 18: Medical Electronics Design, Manufacturing, and Reliability 775
18.1 Introduction 775
18.1.1 Review of Medical Electronic Products Classification 777
18.1.2 Class I Medical Devices 778
18.1.3 Class II Medical Devices 778
18.1.4 Class III Medical Devices 779
18.2 Key Drivers for Growth in Medical Electronics 779
18.2.1 Aging Population 779
18.2.2 Demographic Shift Toward Tech-Competent User Base 780
18.2.3 Target Market Moving from Treatment to Detection and Prevention 781
18.2.4 Availability of Advanced Electrical Content 781
18.3 Design Concepts and Enabling Technologies 783
18.3.1 Low Power Consumption 783
18.3.2 Miniaturization 783
18.3.3 Growth and Standardization of Wireless 785
18.3.4 Sensors, Accelerometers, and Medical Monitoring 786
18.3.5 Advanced Wafer Fabrication Availability 787
18.3.6 Silicon Integration and Electronic Packaging 788
18.4 Implantable Medical Electronics Design and Reliability 790
18.4.1 Implantable Medical Electronic Applications 790
18.4.2 Development Process 792
18.4.3 Environmental Conditions and Constraints 794
18.4.4 Manufacturing Stresses 795
18.4.5 Shipping and Storage 796
18.4.6 Implant Conditions 796
18.4.7 Longevity Requirements 797
18.4.8 Reliability Requirements 797
18.4.9 System Level Failure Modes 799
18.4.10 Commonly Encountered Failure Mechanisms 801
18.5 Qualification 801
18.5.1 Qualification Overview 803
18.5.2 Qualification, Verification, and Validation 804
18.5.3 Manufacturing Process Controls 804
18.5.4 Component and Material Qualification 807
18.5.5 Electronic Module Qualification 808
18.5.6 Finished Device Qualification 809
18.5.7 Supplier Controls 809
18.6 Manufacturing and Process Development 810
18.6.1 Manufacturing Process and Materials 810
18.6.2 Beyond 6-Sigma: Developing Transfer Functions 811
18.6.3 Change Management 813
18.7 Implantable Medical Device Challenges 815
18.7.1 CMOS Scaling 815
18.7.2 Lead-Free Requirements Impact 815
18.7.3 Increasing Device Complexity 816
18.7.4 External System Interfaces 816
18.7.5 Qualification Strategies for the Future 817
References 818
Chapter 19: Flexible and Printed Electronics 820
19.1 Introduction 821
19.2 Flexible Thin-Film Transistor Backplane Technology 821
19.2.1 Hydrogenated Amorphous Silicon TFTs 823
19.2.2 Low-Temperature Polycrystalline Silicon TFTs 825
19.2.3 Oxide TFTs 827
19.2.4 Organic TFTs 832
19.2.5 Fabrication of Flexible TFTs 836
19.2.5.1 Lamination-Debonding Approach 837
19.2.5.2 Coat (Deposit)-Release Approach 837
19.2.5.3 Transfer Approach 840
19.3 Printing Technology for Flexible Electronics Applications 842
19.3.1 Printing Technologies 842
19.3.1.1 Gravure, Gravure-Offset, Flexographic, and Rotary Screen Printing 843
19.3.1.2 Microcontact Printing, Nanoimprint, and Transfer Printing 845
19.3.1.3 Slot-Die and Inkjet Printing 846
19.3.2 Subtractive and Additive Printing Processes 852
19.3.2.1 Subtractive Printing Process 852
19.3.2.2 Additive Printing Process 853
19.4 Outlook 857
References 857
Chapter 20: Silicon Solar Cell Metallization Pastes 862
20.1 Silicon Solar Cells 862
20.1.1 Crystalline Silicon Solar Cells 863
20.1.2 Development Trend 865
20.2 Metallization 865
20.2.1 Front-Side Metallization 866
20.2.1.1 Requirement 866
20.2.1.2 Conventional Silver Pastes and Application Methods 866
20.2.1.3 Novel Silver Pastes with Silver Nanoparticles for Screen Printing 868
20.2.1.4 Glass Frits and Nano-Frits 872
20.2.1.5 Novel Methods for Formation of Silver Electrodes 875
20.2.1.6 Copper/Nickel for Front Metallization 876
20.2.1.7 Screen-Printable Low-Temperature Copper Pastes for Front Busbars 878
20.2.2 Back-Side Metallization 879
20.2.2.1 Aluminum and Aluminum/Silver Pastes for Back Surface Field 879
20.2.2.2 Local BSF for Passivated Emitter and Rear Solar Cells 879
20.2.3 Future of Metallization Materials and Techniques 880
20.3 Solar Cell Modules 881
20.3.1 Components of Solar Cell Modules 881
20.3.2 Manufacturing Process 882
20.3.3 Development Trends 882
References 883
Chapter 21: Nano-metal-Assisted Chemical Etching for Fabricating Semiconductor and Optoelectronic Devices 885
21.1 Introduction 885
21.1.1 Challenges of Top-Down Nanofabrication 887
21.2 Background on Metal-Assisted Chemical Etching (MacEtch) 889
21.2.1 History of MacEtch 889
21.2.2 Chemistry 891
21.2.3 Metal Catalysts 894
21.2.4 Etchant 895
21.2.5 Crystallographic Dependencies 896
21.2.6 Microporous Silicon 897
21.3 Fabrication with MacEtch 899
21.3.1 Pores and Nanowires 900
21.3.2 Channels 902
21.3.3 3D Fabrication 903
21.3.4 Helical/Spiral Structures 907
21.3.5 Electroless Filling MacEtch Templates 912
21.4 Devices and Applications of MacEtch 915
21.4.1 X-Ray Diffractive Optics 915
21.4.2 Thru-Silicon-Via (TSV) 917
21.4.3 MEMS 920
21.4.4 Photovoltaics 921
21.5 Practical Processing Considerations 921
21.5.1 Catalyst and Process Design 921
21.5.2 Etch Stop 922
21.5.3 Fluid Flow Induced Motion and Pre-etch HF Dips 922
21.5.4 Adhesion Layer Thickness 923
21.5.5 Top Layer of Catalyst Stack 924
21.5.6 Catalyst Cleanliness and Etchant Stability 924
References 924
Chapter 22: Characterization of Copper Diffusion in Through Silicon Vias 929
22.1 Cu Diffusion in Through Silicon Vias 929
22.1.1 Barrier Materials for Preventing Cu Diffusion 930
22.1.2 Evaluation of Barrier Layer Stability 931
22.1.3 SIMS Depth Profiling of Cu Diffusion 932
22.2 Effect of Interfacial Multilayer 934
22.2.1 Effect of Insulation Layer 936
22.2.2 Effect of Si Surface Roughness 938
22.2.3 Effects of Barrier Layer and Cu Source Layer 939
22.3 Phase Transition in Thermal Annealing 941
22.4 Factor Rank for Cu Diffusion 945
22.4.1 DOE for Rank Analysis 946
22.4.2 Diffusion Depth versus Annealing Time 949
22.4.3 Rank Analysis of Different Layers 950
References 954
Index 958