Guide to RISC Processors

for Programmers and Engineers

****

Buch | Hardcover
388 Seiten
2005
Springer-Verlag New York Inc.
978-0-387-21017-9 (ISBN)

Lese- und Medienproben

Guide to RISC Processors - Sivarama P. Dandamudi
96,29 inkl. MwSt
Recently, there has been a trend toward processors based on the RISC (Reduced Instruction Set Computer) design. Initial chapters explain differences between the CISC and RISC designs, and the core RISC design principles are clearly discussed.
Recently, there has been a trend toward processors based on the RISC (Reduced Instruction Set Computer) design. This is an accessible and all-encompassing compendium on RISC processors, introducing five of them: MIPS, SPARC, PowerPC, ARM, and Intel's 64-bit Itanium. Initial chapters explain differences between the CISC and RISC designs, and the core RISC design principles are clearly discussed. Later chapters provide instruction on MIPS assembly language programming, so that readers can readily learn the concepts and principles introduced earlier. Professionals, programmers, and students in computer architecture and programming courses will find the guide an essential resource.

Overview.- Processor Design Issues.- RISC Principles.- Architectures.- MIPS Architecture.- SPARC Architecture.- PowerPC Architecture.- Itanium Architecture.- ARM Architecture.- MIPS Assembly Language.- SPIM Simulator and Debugger.- Assembly Language Overview.- Procedures and the Stack.- Addressing Modes.- Arithmetic Instructions.- Conditional Execution.- Logical and Shift Operations.- Recursion.- Floating-Point Operations.

Zusatzinfo 80 Illustrations, black and white; XVI, 388 p. 80 illus.
Verlagsort New York, NY
Sprache englisch
Maße 178 x 254 mm
Themenwelt Mathematik / Informatik Informatik Software Entwicklung
Informatik Theorie / Studium Algorithmen
Informatik Weitere Themen Hardware
Technik Elektrotechnik / Energietechnik
ISBN-10 0-387-21017-2 / 0387210172
ISBN-13 978-0-387-21017-9 / 9780387210179
Zustand Neuware
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