Applied Formal Verification
McGraw-Hill Professional (Verlag)
978-0-07-144372-2 (ISBN)
Formal verification is a powerful new digital design methodIn this cutting-edge tutorial, two of the field's best known authors team up to show designers how to efficiently apply Formal Verification, along with hardware description languages like Verilog and VHDL, to more efficiently solve real-world design problems.
Douglas L. Perry (Mountain View, CA) is the Director of Verification IP for Jasper Design Automation, Inc. He is the author of four editions of McGraw-Hills VHDL. Harry Foster (Mountain View, CA) serves as Chairman of the Accellera Formal Verification Technical Committee, which is currently defining the PSL property specification language standard. He is co-author of the new Kluwer Academic Publishers book Assertion-Based Design. Prior to joining Jasper Design, Harry was Verplex Systems' Chief Architect.
PREFACEChapter 1: Introduction to VerificationChapter 2: Verification ProcessChapter 3: Current Verification TechniquesChapter 4: Introduction to Formal TechniquesChapter 5: Formal Basics and DefinitionsChapter 6: Property SpecificationChapter 7: The Formal Test Plan ProcessChapter 8: Techniques for Proving PropertiesChapter 9: Final System SimulationAPPENDIX A: IEEE 1850 PSL PROPERTY SPECIFICATION LANGUAGEAPPENDIX B: IEEE 1800 SYSTEM VERILOG ASSERTIONSBIBLIOGRAPHYINDEX
| Erscheint lt. Verlag | 16.5.2005 |
|---|---|
| Zusatzinfo | 75 Illustrations, unspecified |
| Sprache | englisch |
| Maße | 155 x 231 mm |
| Gewicht | 508 g |
| Themenwelt | Technik ► Elektrotechnik / Energietechnik |
| ISBN-10 | 0-07-144372-X / 007144372X |
| ISBN-13 | 978-0-07-144372-2 / 9780071443722 |
| Zustand | Neuware |
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