Power-Aware Computer Systems
Springer Berlin (Verlag)
978-3-540-24031-0 (ISBN)
Compilers.- Runtime Biased Pointer Reuse Analysis and Its Application to Energy Efficiency.- Inter-program Compilation for Disk Energy Reduction.- Embedded Systems.- Energy Consumption in Mobile Devices: Why Future Systems Need Requirements-Aware Energy Scale-Down.- Efficient Scratchpad Allocation Algorithms for Energy Constrained Embedded Systems.- Online Prediction of Battery Lifetime for Embedded and Mobile Devices.- Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture.- Heterogeneous Wireless Network Management.- Microarchitectural Techniques.- "Look It Up" or "Do the Math": An Energy, Area, and Timing Analysis of Instruction Reuse and Memoization.- CPU Packing for Multiprocessor Power Reduction.- Exploring the Potential of Architecture-Level Power Optimizations.- Coupled Power and Thermal Simulation with Active Cooling.- Cache and Memory Systems.- The Synergy Between Power-Aware Memory Systems and Processor Voltage Scaling.- Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches.- PARROT: Power Awareness Through Selective Dynamically Optimized Traces.
Erscheint lt. Verlag | 17.12.2004 |
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Reihe/Serie | Lecture Notes in Computer Science |
Zusatzinfo | X, 215 p. |
Verlagsort | Berlin |
Sprache | englisch |
Maße | 155 x 235 mm |
Gewicht | 350 g |
Themenwelt | Mathematik / Informatik ► Informatik |
Technik ► Elektrotechnik / Energietechnik | |
Schlagworte | Circuit Design • Compiler • Computer • Embedded System • Embedded Systems • Energy Dissipation • Hardware Design • low power consumption • Performance Analysis • Power-Aware Computer Systems • Power-Aware Computing • power-aware memory systems • power optimization • processor design |
ISBN-10 | 3-540-24031-4 / 3540240314 |
ISBN-13 | 978-3-540-24031-0 / 9783540240310 |
Zustand | Neuware |
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