Logically Determined Design – Clockless Systems Design with NULL Convention Logic

KARL M. FANT is President of Theseus Research, Inc. After serving as a Research Fellow at Honeywell, he co-founded Theseus Research and then Theseus Logic, which is now commercializing NULL Convention LogicTM. He holds twenty-nine patents and has published numerous papers.

Preface. Acknowledgments. 1. Trusting Logic. 1.1 Mathematicianless Enlivenment of Logic Expression. 1.2 Emulating the Mathematician. 1.3 Supplementing the Expressivity of Boolean Logic. 1.4 Defining a Sufficiently Expressive Logic. 1.5 The Logically Determined System. 1.6 Trusting the Logic: A Methodology of Logical Confidence. 1.7 Summary. 1.8 Exercises. 2. A Sufficiently Expressive Logic. 2.1 Searching for a New Logic. 2.2 Deriving a 3 Value Logic. 2.3 Deriving a 2 Value Logic. 2.4 Compromising Logical Completeness. 2.5 Summary. 3. The Structure of Logically Determined Systems. 3.1 The Cycle. 3.2 Basic Pipeline Structures. 3.3 Control Variables and Wavefront Steering. 3.4 The Logically Determined System. 3.5 Initialization. 3.6 Testing. 3.7 Summary. 3.8 Exercises. 4. 2NCL Combinational Expression. 4.1 Function Classification. 4.2 The Library of 2NCL Operators. 4.3 2NCL Combinational Expression. 4.4 Example 1: Binary Plus Trinary to Quaternary Adder. 4.5 Example 2: Logic Unit. 4.6 Example 3: Minterm Construction. 4.7 Example 4: A Binary Clipper. 4.8 Example 5: A Code Detector. 4.9 Completeness Sufficiency. 4.10 Greater Combinational Composition. 4.11 Directly Mapping Boolean Combinational Expressions. 4.12 Summary. 4.13 Exercises. 5. Cycle Granularity. 5.1 Partitioning Combinational Expressions. 5.2 Partitioning the Data Path. 5.3 Two-dimensional Pipelining: Orthogonal Pipelining Across a Data Path. 5.4 2D Wavefront Behavior. 5.5 2D Pipelined Operations. 5.6 Summary. 5.7 Exercises. 6. Memory Elements. 6.1 The Ring Register. 6.2 Complex Function Registers. 6.3 The Consume/Produce Register Structure. 6.4 The Register File. 6.5 Delay Pipeline Memory. 6.6 Delay Tower. 6.7 FIFO Tower. 6.8 Stack Tower. 6.9 Wrapper for Standard Memory Modules. 6.10 Exercises. 7. State Machines. 7.1 Basic State Machine Structure. 7.2 Exercises. 8. Busses and Networks. 8.1 The Bus. 8.2 A Fan-out Steering Tree. 8.3 Fan-in Steering Trees Do Not Work. 8.4 Arbitrated Steering Structures. 8.5 Concurrent Crossbar Network. 8.6 Exercises. 9. Multi-value Numeric Design. 9.1 Numeric Representation. 9.2 A Quaternary ALU. 9.3 A Binary ALU. 9.4 Comparison. 9.5 Summary. 9.6 Exercises. 10. The Shadow Model of Pipeline Behavior. 10.1 Pipeline Structure. 10.2 The Pipeline Simulation Model. 10.3 Delays Affecting Throughput. 10.4 The Shadow Model. 10.5 The Value of the Shadow Model. 10.6 Exercises. 11. Pipeline Buffering. 11.1 Enhancing Throughput. 11.2 Buffering for Constant Rate Throughput. 11.3 Summary of Buffering. 11.4 Exercises. 12. Ring Behavior. 12.1 The Pipeline Ring. 12.2 Wavefront-limited Ring Behavior. 12.3 The Cycle-to-Wavefront Ratio. 12.4 Ring Signal Behavior. 13. Interacting Pipeline Structures. 13.1 Preliminaries. 13.2 Example 1: The Basics of a Two-pipeline Structure. 13.3 Example 2: A Wavefront Delay Structure. 13.4 Example 3: Reducing the Period of the Slowest Cycle. 13.5 Exercises. 14. Complex Pipeline Structures. 14.1 Linear Feedback Shift Register Example. 14.2 Grafting Pipelines. 14.3 The LFSR with a Slow Cycle. 14.4 Summary. 14.5 Exercises. Appendix A: Logically Determined Wavefront Flow. A.1 Synchronization. A.2 Wavefronts and Bubbles. A.3 Wavefront Propagation. A.4 Extended Simulation of Wavefront Flow. A.5 Wavefront and Bubble Behavior in a System. Appendix B: Playing with 2NCL. B.1 The SR Flip-flop Implementations. B.2 Initialization. B.3 Auto-produce and Auto-consume. Appendix C: Pipeline Simulation. References. Index.